Abstract: A system and method for modulation diversity uses interleaving. Code bits are placed into groups and are then shuffled within each group.

Abstract: An apparatus, a method, and a computer program are provided to disable clock distribution. In microprocessors, the clock distribution system can account for a substantial amount of power consumption. Disabling the clock distribution system, however, has been difficult because of the usual requirement for a separate clock for control logic. Therefore, combinational logic can be employed to disrupt the clock distribution and allow a processor to be awakened without a need for a separate clock.

Abstract: A system and method for frequency diversity uses interleaving. Subcarriers of an interlace are interleaved in a bit reversal fashion and the interlaces are interleaved in the bit reversal fashion.

Abstract: A cell library which enables reduced quantization over-design in large scale circuit design is provided. Library cells having the same cell function have drive strengths selected to provide delays about equal to a predetermined set of design delays, at a nominal load corresponding to the cell function. In contrast, conventional cell libraries typically have drive strengths which correspond to a predetermined set of cell physical areas. Preferably, the spacing between adjacent design delays is a non-decreasing function of cell drive strength. Such spacing reduces quantization induced over-design compared to conventional cell libraries which have a design delay spacing that is a decreasing function of cell drive strength. On-chip clock distribution is an important application where cell libraries of the invention can provide significant advantages.

Abstract: An integrated circuit die is disclosed including a temperature detection circuit and a memory configured to store calibration data. The temperature detection circuit is operatively coupled to the memory, and receives an input signal. The temperature detection circuit is configured to produce an output signal dependent upon the input signal and indicative of whether a temperature of the integrated circuit die is greater than a selected temperature. During a normal operating mode of the integrated circuit die the input signal comprises the calibration data. A system and methods for calibrating the temperature detection circuit are also described.

Abstract: A method, an apparatus, and a computer program are provided to reduce transient current swings during mode transitions. Traditionally, transient supply voltage fluctuations on a chip account for a large portion of the power supply. The number of series inductances and resistances are typically minimized, while adding large decoupling capacitances between the supply voltage and ground. However, situations may arise where reduction of series inductances and resistances cannot be accomplished. Therefore, to assist in controlling the transient current swings, reduction of clocking frequencies are performed in a controlled manner.

Abstract: A lens includes a diffractive surface having an etched structure and a refractive surface having a curved structure. The lens reduces chromatic aberration of incident light and extends depth of focus. In one alternative, the etched structure is a calculated phase pattern or a pattern that is embossed or diamond tuned. In another alternative, the curved structure is convex shaped or concave shaped. In yet another alternative, the lens is an imaging lens wherein high lateral resolution of incident light is preserved.

Abstract: The present invention provides for a circuit for transitioning clocking speeds. A counter is coupled to the clocking means. A comparator is coupled to an output of the counter. A first divider is coupled to the output of the counter. A processor means is coupled to the output of the first divider, thereby lessening current surges.

Abstract: The present invention provides for reducing current spikes in a circuit when changing clocking frequencies. A first frequency is applied to a clock distribution network. A final frequency is selected. The first frequency is applied to a logic element over the clock distribution network. A hold signal is applied to the logic element. The clock rate of the clock distribution network is changed from the first frequency to the final frequency. The hold signal is unapplied to the logic element.

Abstract: An apparatus, a method, and a computer program are provided for the generation of constant incremental increases while changing core clock frequencies. In computer systems, oftentimes frequency changes are useful. Maintaining the clocking ability of the computer system, though, can be a difficult task. To maintain the time keeping ability, time base logic is utilized with the free-running clock, which can be frequency limited. However, a plurality of communication channels in conjunction with an adder system is employed to effectively adjust for an ever increasing frequency to allow for a effective timekeeping regardless of the core frequency.

Abstract: A method and system for the dynamic interactive display of digital images, comprising client and server applications working together over the Internet or over other similar modes of digital data transmission to collect, store, select, present, distribute and manage information for digital images, including photographs, pictures, videos, movies and other forms of digital media. The present invention achieves these functions through user-friendly dynamic interactive graphical user interfaces that are readily accessible over the Internet from a wide variety of devices used for digital communication.

Abstract: The present invention provides for controlling the power consumption of an element. A first power control command is issued by software for the element. It is determined if the power control command corresponds to an allowable power control state for that element as defined by the hardware. If the power control command is not an allowable power control state for that element, the hardware sets the power control at a higher level than the power control state issued by the software. The software is real time software, and the software also sets minimally acceptable activity control states. A hierarchy of power consumption is defined for different elements of a chip by software, which provides the minimum level of power consumption by any element or sub-element on a chip.

Abstract: An axial sealing mechanism of a scroll compressor includes a housing, a scroll device, and a floating seal member with a recess portion and a central channel. The housing includes a first shell and a second shell. The first shell has a receiving chamber. A partition is disposed inside the receiving chamber. The scroll device includes a fixed scroll and an orbiting scroll. A plurality of compression pockets is formed between the fixed scroll and the orbiting scroll. The fixed scroll has a protruding portion with a plurality of orifices. The recess portion of the floating seal member receives the protruding portion of the fixed scroll. Seal elements are respectively secured to the floating seal member and the fixed scroll. An intermediate pressure room is thereby formed between the float seal element and the fixed scroll.

Abstract: In an OFDM system, multiple (M) interlaces are defined for M non-overlapping sets of frequency subbands, and M slots with fixed indices are also defined. Data streams and pilot are mapped to slots, which are in turn mapped to interlaces based on a slot-to-interlace mapping scheme that can achieve frequency diversity and good performance for all slots. At a transmitter, a slot-to-interlace converter maps the slots to the interlaces. The slot-to-interlace converter includes multiple multiplexers and a control unit. The multiplexers map the M slots to the M interlaces based on the slot-to-interlace mapping scheme. The control unit generates at least one control signal for the multiplexers. The multiplexers may be arranged and controlled in various manners depending on the slot-to-interlace mapping scheme. At a receiver, a complementary interlace-to-slot converter maps the interlaces to the slots.

Abstract: A cell library which enables reduced quantization over-design in large scale circuit design is provided. Library cells having the same cell function have drive strengths selected to provide delays about equal to a predetermined set of design delays, at a nominal load corresponding to the cell function. In contrast, conventional cell libraries typically have drive strengths which correspond to a predetermined set of cell physical areas. Preferably, the spacing between adjacent design delays is a non-decreasing function of cell drive strength. Such spacing reduces quantization induced over-design compared to conventional cell libraries which have a design delay spacing that is a decreasing function of cell drive strength.

Abstract: A simple, approximate power optimization in connection with automatic large scale circuit design using a cell library is provided. The cell library of the present invention provides active region information for each cell, and preferably also provides conventional parameters such as cell physical area and cell performance information. Typically, several cells having differing parameters correspond to each cell function provided by the library. A cost function is defined which depends on active region information, and can also depend on physical area and performance. A cell design including cells selected from the library is optimized by substitution of functionally equivalent cells from the library to minimize the cost function. Minimization of active region area provides a simple way to approximately minimize power consumption. Optionally, a second optimization can be performed with a higher fidelity power model using the approximately power-minimized design as a starting point.

Abstract: A simple, approximate power optimization in connection with automatic large scale circuit design using a cell library is provided. The cell library of the present invention provides active region information for each cell, and preferably also provides conventional parameters such as cell physical area and cell performance information. Typically, several cells having differing parameters correspond to each cell function provided by the library. A cost function is defined which depends on active region information, and can also depend on physical area and performance. A cell design including cells selected from the library is optimized by substitution of functionally equivalent cells from the library to minimize the cost function. Minimization of active region area provides a simple way to approximately minimize power consumption. Optionally, a second optimization can be performed with a higher fidelity power model using the approximately power-minimized design as a starting point.

Abstract: The present invention provides for determining a temperature in a chip. A voltage across a thermal diode is generated. It is then determined whether the voltage across the first thermal diode exceeds a threshold value. The voltage is correlated with a range of values. The determination of whether the voltage across the thermal diode exceeds the threshold value is correlated with the correlation of the voltage with a range of values. Through the use of voltage level sensors, the use of C4 input/output pins are avoided.

Abstract: In a wireless communication system, a scheduler (100) determines (306) a first set of modulation and coding schemes (MCSs), each of which produces a maximum data rate for a first user, in accordance with available resource constraints (304) of the wireless communication system. The scheduler then forms, for each MCS of the first set, a second set of MCSs that produces the maximum data rate for a second user in accordance with a first residual resource (314) that remains when applying that MCS to the first user, thereby producing (316) a group of second sets of MCSs. After producing the group of second sets, the scheduler selects (324), from the first set and for the first user, a first optimal MCS corresponding to one of the group of second sets that allows a highest maximum data rate for the second user.