Abstract: To address problems associated with power management of electronic devices, the subject matter described herein provides improved power management solutions that enable CPUs and other electronic components to characterize real-time power consumption. This may be used to assess an effect of added platform level features after factory testing, and may be used to improve or optimize system performance. These solutions may include an accurate platform-independent integrated voltage measurement, dedicated to a reliable absolute voltage measurement that may be used for multiple purposes. The subject matter described herein proposes a combination of a voltage detector and an algorithm implemented in the electronic component (e.g., CPU) that may be used to compensate for voltage variations due to tolerances or guard bands, and may be used to detect discrepancies of underreporting or overreporting of current information by the platform VR.

Abstract: Embodiments of the present invention provide a voltage protection apparatus (130, 160, 205, 630, 730), comprising an input (165, 210, 610, 710) to receive an input voltage provided to a processor (120), an output (190, 260, 680, 760) to output a throttle signal to the processor (120), a filter circuit (180, 240, 640, 660, 740) to filter the input voltage provided to the processor (120) to provide a filtered input voltage, and a first circuit (170, 230, 630, 650, 73) to compare the filtered input voltage to a first threshold voltage (175, 235, 635, 645, 735) and to cause the output (190, 260, 680, 760) to provide the throttle signal to the processor (120) indicative of the filtered input voltage dropping below the first threshold voltage.

Abstract: A supply voltage may be set using a local voltage regulator, such as a Digital Linear Voltage Regulators (DLVR). A DLVR may include a compensator, and the performance of the compensator may be affected by a dropout (DO) voltage. To improve the performance of a compensator, a number of compensator calculations may be pre-calculated to reduce the complexity of remaining real-time computations and enable compensator calculations to be completed within a single DLVR clock cycle. A DLVR may include a sense filter, and the DLVR transfer function (TF) may be modified using dynamic shaping of open loop gain and pole locations of a sense filter. The DO range associated with the DLVR TF may be changed according to a monitored DO(t) to reduce the sensitivity of a domain VMIN on dropout, which reduces power consumption, increases performance, and enables simplification of test flows.

Abstract: Some embodiments include an apparatus including a first node in a voltage regulator, a second node in the voltage regulator, and a power stage to receive a first voltage from the first node and provide a second voltage at the second node. The power stage includes a first circuit path and a second circuit path coupled in parallel with each other between the first and second nodes. The first circuit path includes a first number of at least one transistor coupled between the first and second nodes The second circuit path includes a second number of at least one transistor between the first and second nodes. Wherein the first number is unequal to the second number.

Abstract: A power supply architecture combines the benefits of a traditional single stage power delivery, when there are no additional power losses in the integrated VR with low VID and low CPU losses of FIVR (fully integrated voltage regulator) and D-LVR (digital linear voltage regulator). The D-LVR is not in series with the main power flow, but in parallel. By placing the digital-LVR in parallel to a primary VR (e.g., motherboard VR), the CPU VID is lowered and the processor core power consumption is lowered. The power supply architecture reduces the guard band for input power supply level, thereby reducing the overall power consumption because the motherboard VR specifications can be relaxed, saving cost and power. The power supply architecture drastically increases the CPU performance at a small extra cost for the silicon and low complexity of tuning.

Abstract: Described is an apparatus and method to prevent a processor from abruptly shutting down by proactive power management. The apparatus comprises a power supply rail to receive a current and a voltage from a power supply generator (e.g., a DC-DC converter, and low dropout regulator); a processor coupled to the power supply rail, wherein the processor is to operate with a current and a voltage provided by the power supply rail; and an interface to receive a request to throttle one or more performance parameters of the processor when a monitored current through the power supply rail or a monitored voltage on the power supply rail crosses a threshold current or a threshold voltage, respectively, wherein the threshold current is below a catastrophic threshold current of a voltage regulator, or wherein the threshold voltage is above a catastrophic threshold voltage of the processor.

Abstract: An apparatus is provided which comprises: a first voltage regulator; a second voltage regulator; and a switch to selectively couple the first voltage regulator to the second voltage regulator, such that a first output node of the first voltage regulator is temporarily coupled to a second output node of the second voltage regulator via the switch.

Abstract: The circuits and methods described herein provide technical solutions for technical problems facing power driver circuits. To reduce or eliminate effects associated with a gate capacitance discharge current and inconsistent effective Vbias, the discharge process may be split into two phases. During a first phase, the transistor gate charge is drained into ground through a large path gate. The ground (GND) features a very low impedance, hence the resulting ?Vbias(t)|phase_1 is negligible even for high discharge currents. The transistor gate node voltage (Vgate) is constantly monitored, and the discharge process switches from the first phase to the second phase when Vgate transgresses a bias voltage threshold based on the target value of Vbias. To switch from the first phase to the second phase, the current path into GND is cut by switching its path gate to an OFF state, and an alternative path is enabled between transistor gate charge and Vbias.

Abstract: A power supply architecture combines the benefits of a traditional single stage power delivery, when there are no additional power losses in the integrated VR with low VID and low CPU losses of FIVR (fully integrated voltage regulator) and D-LVR (digital linear voltage regulator). The D-LVR is not in series with the main power flow, but in parallel. By placing the digital-LVR in parallel to a primary VR (e.g., motherboard VR), the CPU VID is lowered and the processor core power consumption is lowered. The power supply architecture reduces the guard band for input power supply level, thereby reducing the overall power consumption because the motherboard VR specifications can be relaxed, saving cost and power. The power supply architecture drastically increases the CPU performance at a small extra cost for the silicon and low complexity of tuning.

Abstract: Methods and systems to adjust a resistance between a supply grid and a power-gated grid during an active state of a power-gated circuitry in response to load changes in the circuitry to maintain a relatively consistent IR droop. Subsets of power gates (PGs) may be selectively enabled and disabled based on changes in a load factor, such as a voltage, which may be monitored at a gated power distribution grid and/or proximate to a transistor gate within the power-gated circuitry. The adjusting may be performed to minimize a difference between the monitored voltage and a reference, such as with successive approximation or CMS software. PG subsets may be distributed within one or more layers of an integrated circuit (IC) die and may be selectively enabled/disabled based on location. PGs may be embedded within lower layers of an integrated circuit (IC) die, such as within metal layers of the IC die.

Abstract: Described is an apparatus which comprises: a first power supply node to supply input power supply; a power transistor coupled to the first power supply node; a multiplexer to selectively control gate terminal of the power transistor according to whether the power transistor is to operate as part of a low dropout voltage regulator (LDO-VR) or is to operate as a digital switch; and a second power supply node coupled to the power transistor, the second power supply node to provide power supply to a load from the power transistor.

Abstract: A power-gate circuit includes a power-gate transistor operable to switch to decouple a first supply voltage from a second supply voltage during an idle mode, and to couple the first supply voltage to the second supply voltage during a full operational mode. Part of the charge stored at a gate terminal of the power-gate transistor, would have been otherwise flushed to ground while turning on the power-gate transistor, is routed to the rail of the second supply voltage of the logic block. Part of the charge on the rail of the second supply voltage is used to charge the gate terminal of the power-gate transistor to deactivate the power-gate transistor if the logic block goes to the idle mode. Energy is saved both ways because of the charge recycling and the ability to use the power-gate circuit even in cases where the duration of the idle mode may be short.

Abstract: In some examples, a voltage protection apparatus includes a circuit to compare an input voltage of a processor to a threshold voltage, and to provide a throttle signal to the processor if the input voltage of the processor droops below the threshold voltage. The processor input voltage can then be set to a lower voltage and the processor power can thus be lowered.

Abstract: Disclosed herein are structures and techniques for exposing circuitry in die testing. For example, in some embodiments, an integrated circuit (IC) die may include: first conductive contacts at a first face of the die; second conductive contacts at a second face of the die, wherein the second face is opposite to the first face; circuitry; and a switch coupled between the second conductive contacts and the circuitry, wherein the circuitry is not electrically exposed by the second conductive contacts when the switch is open, and the circuitry is electrically exposed by the second conductive contacts when the switch is closed.

Abstract: Methods and systems to adjust a resistance between a supply grid and a power-gated grid during an active state of a power-gated circuitry in response to load changes in the circuitry to maintain a relatively consistent IR droop. Subsets of power gates (PGs) may be selectively enabled and disabled based on changes in a load factor, such as a voltage, which may be monitored at a gated power distribution grid and/or proximate to a transistor gate within the power-gated circuitry. The adjusting may be performed to minimize a difference between the monitored voltage and a reference, such as with successive approximation or CMS software. PG subsets may be distributed within one or more layers of an integrated circuit (IC) die and may be selectively enabled/disabled based on location. PGs may be embedded within lower layers of an integrated circuit (IC) die, such as within metal layers of the IC die.

Abstract: Described is an apparatus and method to prevent a processor from abruptly shutting down by proactive power management. The apparatus comprises a power supply rail to receive a current and a voltage from a power supply generator (e.g., a DC-DC converter, and low dropout regulator); a processor coupled to the power supply rail, wherein the processor is to operate with a current and a voltage provided by the power supply rail; and an interface to receive a request to throttle one or more performance parameters of the processor when a monitored current through the power supply rail or a monitored voltage on the power supply rail crosses a threshold current or a threshold voltage, respectively, wherein the threshold current is below a catastrophic threshold current of a voltage regulator, or wherein the threshold voltage is above a catastrophic threshold voltage of the processor.

Abstract: Methods and systems to adjust a resistance between a supply grid and a power-gated grid during an active state of a power-gated circuitry in response to load changes in the circuitry to maintain a relatively consistent IR droop. Subsets of power gates (PGs) may be selectively enabled and disabled based on changes in a load factor, such as a voltage, which may be monitored at a gated power distribution grid and/or proximate to a transistor gate within the power-gated circuitry. The adjusting may be performed to minimize a difference between the monitored voltage and a reference, such as with successive approximation or CMS software. PG subsets may be distributed within one or more layers of an integrated circuit (IC) die and may be selectively enabled/disabled based on location. PGs may be embedded within lower layers of an integrated circuit (IC) die, such as within metal layers of the IC die.

Abstract: Described herein is an integrated circuit which comprises: a switching voltage regulator (SVR), having one or more bridge drivers, to provide regulated power supply to a plurality of power domains; and a power control unit (PCU) operable to adjust switching frequencies of the SVR according to states of the plurality of power domains, wherein drive strength or active phase count of the one or more bridge drivers is also adjusted by a logic unit of the SVR when the switching frequencies of the SVR are adjusted.

Abstract: An apparatus is provided which comprises: a first voltage regulator; a second voltage regulator; and a switch to selectively couple the first voltage regulator to the second voltage regulator, such that a first output node of the first voltage regulator is temporarily coupled to a second output node of the second voltage regulator via the switch.

Abstract: Described is an apparatus which comprises: a first power supply node to supply input power supply; a power transistor coupled to the first power supply node; a multiplexer to selectively control gate terminal of the power transistor according to whether the power transistor is to operate as part of a low dropout voltage regulator (LDO-VR) or is to operate as a digital switch; and a second power supply node coupled to the power transistor, the second power supply node to provide power supply to a load from the power transistor.