Patents by Inventor Michael Zelikson

Michael Zelikson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10536139
    Abstract: A power-gate circuit includes a power-gate transistor operable to switch to decouple a first supply voltage from a second supply voltage during an idle mode, and to couple the first supply voltage to the second supply voltage during a full operational mode. Part of the charge stored at a gate terminal of the power-gate transistor, would have been otherwise flushed to ground while turning on the power-gate transistor, is routed to the rail of the second supply voltage of the logic block. Part of the charge on the rail of the second supply voltage is used to charge the gate terminal of the power-gate transistor to deactivate the power-gate transistor if the logic block goes to the idle mode. Energy is saved both ways because of the charge recycling and the ability to use the power-gate circuit even in cases where the duration of the idle mode may be short.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: January 14, 2020
    Assignee: Intel Corporation
    Inventors: Shai Rotem, Norbert Unger, Michael Zelikson
  • Publication number: 20190377405
    Abstract: In some examples, a voltage protection apparatus includes a circuit to compare an input voltage of a processor to a threshold voltage, and to provide a throttle signal to the processor if the input voltage of the processor droops below the threshold voltage. The processor input voltage can then be set to a lower voltage and the processor power can thus be lowered.
    Type: Application
    Filed: March 29, 2019
    Publication date: December 12, 2019
    Applicant: Intel Corporation
    Inventors: Alexander B. Uan-Zo-li, Eugene Gorbatov, Philip R. Lehwalder, Michael Zelikson, Sameer Shekhar, Nimrod Angel, Jonathan Douglas, Muhammad Abozaed, Alan Hallberg, Douglas Huard, Edward Burton, Merwin Brown
  • Publication number: 20190287868
    Abstract: Disclosed herein are structures and techniques for exposing circuitry in die testing. For example, in some embodiments, an integrated circuit (IC) die may include: first conductive contacts at a first face of the die; second conductive contacts at a second face of the die, wherein the second face is opposite to the first face; circuitry; and a switch coupled between the second conductive contacts and the circuitry, wherein the circuitry is not electrically exposed by the second conductive contacts when the switch is open, and the circuitry is electrically exposed by the second conductive contacts when the switch is closed.
    Type: Application
    Filed: March 15, 2018
    Publication date: September 19, 2019
    Applicant: Intel Corporation
    Inventor: Michael Zelikson
  • Publication number: 20190204886
    Abstract: Methods and systems to adjust a resistance between a supply grid and a power-gated grid during an active state of a power-gated circuitry in response to load changes in the circuitry to maintain a relatively consistent IR droop. Subsets of power gates (PGs) may be selectively enabled and disabled based on changes in a load factor, such as a voltage, which may be monitored at a gated power distribution grid and/or proximate to a transistor gate within the power-gated circuitry. The adjusting may be performed to minimize a difference between the monitored voltage and a reference, such as with successive approximation or CMS software. PG subsets may be distributed within one or more layers of an integrated circuit (IC) die and may be selectively enabled/disabled based on location. PGs may be embedded within lower layers of an integrated circuit (IC) die, such as within metal layers of the IC die.
    Type: Application
    Filed: March 11, 2019
    Publication date: July 4, 2019
    Applicant: Intel Corporation
    Inventors: Michael Zelikson, Vjekoslav Svilan, Norbert Unger, Shai Rotem
  • Publication number: 20190146569
    Abstract: Described is an apparatus and method to prevent a processor from abruptly shutting down by proactive power management. The apparatus comprises a power supply rail to receive a current and a voltage from a power supply generator (e.g., a DC-DC converter, and low dropout regulator); a processor coupled to the power supply rail, wherein the processor is to operate with a current and a voltage provided by the power supply rail; and an interface to receive a request to throttle one or more performance parameters of the processor when a monitored current through the power supply rail or a monitored voltage on the power supply rail crosses a threshold current or a threshold voltage, respectively, wherein the threshold current is below a catastrophic threshold current of a voltage regulator, or wherein the threshold voltage is above a catastrophic threshold voltage of the processor.
    Type: Application
    Filed: December 21, 2018
    Publication date: May 16, 2019
    Applicant: Intel Corporation
    Inventors: Chee Lim NGE, Amit JAIN, Anant DEVAL, Nimrod ANGEL, Fabrice PAILLET, Michael ZELIKSON, Sergio Carlo RODRIGUEZ
  • Patent number: 10228738
    Abstract: Methods and systems to adjust a resistance between a supply grid and a power-gated grid during an active state of a power-gated circuitry in response to load changes in the circuitry to maintain a relatively consistent IR droop. Subsets of power gates (PGs) may be selectively enabled and disabled based on changes in a load factor, such as a voltage, which may be monitored at a gated power distribution grid and/or proximate to a transistor gate within the power-gated circuitry. The adjusting may be performed to minimize a difference between the monitored voltage and a reference, such as with successive approximation or CMS software. PG subsets may be distributed within one or more layers of an integrated circuit (IC) die and may be selectively enabled/disabled based on location. PGs may be embedded within lower layers of an integrated circuit (IC) die, such as within metal layers of the IC die.
    Type: Grant
    Filed: December 27, 2011
    Date of Patent: March 12, 2019
    Assignee: Intel Corporation
    Inventors: Michael Zelikson, Vjekoslav Svilan, Norbert Unger, Shai Rotem
  • Patent number: 10203742
    Abstract: Described herein is an integrated circuit which comprises: a switching voltage regulator (SVR), having one or more bridge drivers, to provide regulated power supply to a plurality of power domains; and a power control unit (PCU) operable to adjust switching frequencies of the SVR according to states of the plurality of power domains, wherein drive strength or active phase count of the one or more bridge drivers is also adjusted by a logic unit of the SVR when the switching frequencies of the SVR are adjusted.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: February 12, 2019
    Assignee: INTEL CORPORATION
    Inventors: Gregory Sizikov, Michael Zelikson, Efraim Rotem, Eyal Fayneh
  • Publication number: 20180375438
    Abstract: An apparatus is provided which comprises: a first voltage regulator; a second voltage regulator; and a switch to selectively couple the first voltage regulator to the second voltage regulator, such that a first output node of the first voltage regulator is temporarily coupled to a second output node of the second voltage regulator via the switch.
    Type: Application
    Filed: June 23, 2017
    Publication date: December 27, 2018
    Inventors: Sameer Shekhar, Amit K. Jain, Alexander Waizman, Michael Zelikson, Chin Lee Kuan
  • Patent number: 10156859
    Abstract: Described is an apparatus which comprises: a first power supply node to supply input power supply; a power transistor coupled to the first power supply node; a multiplexer to selectively control gate terminal of the power transistor according to whether the power transistor is to operate as part of a low dropout voltage regulator (LDO-VR) or is to operate as a digital switch; and a second power supply node coupled to the power transistor, the second power supply node to provide power supply to a load from the power transistor.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: December 18, 2018
    Assignee: Intel Corporation
    Inventors: Kosta Luria, Alexander Lyakhov, Joseph Shor, Michael Zelikson
  • Publication number: 20180307257
    Abstract: Described is an apparatus which comprises: a first power supply node to supply input power supply; a power transistor coupled to the first power supply node; a multiplexer to selectively control gate terminal of the power transistor according to whether the power transistor is to operate as part of a low dropout voltage regulator (LDO-VR) or is to operate as a digital switch; and a second power supply node coupled to the power transistor, the second power supply node to provide power supply to a load from the power transistor.
    Type: Application
    Filed: June 18, 2018
    Publication date: October 25, 2018
    Applicant: Intel Corporation
    Inventors: Kosta Luria, Alexander Lyakhov, Joseph Shor, Michael Zelikson
  • Publication number: 20180241384
    Abstract: A power-gate circuit includes a power-gate transistor operable to switch to decouple a first supply voltage from a second supply voltage during an idle mode, and to couple the first supply voltage to the second supply voltage during a full operational mode. Part of the charge stored at a gate terminal of the power-gate transistor, would have been otherwise flushed to ground while turning on the power-gate transistor, is routed to the rail of the second supply voltage of the logic block. Part of the charge on the rail of the second supply voltage is used to charge the gate terminal of the power-gate transistor to deactivate the power-gate transistor if the logic block goes to the idle mode. Energy is saved both ways because of the charge recycling and the ability to use the power-gate circuit even in cases where the duration of the idle mode may be short.
    Type: Application
    Filed: April 20, 2018
    Publication date: August 23, 2018
    Inventors: Shai Rotem, Norbert Unger, Michael Zelikson
  • Publication number: 20180173298
    Abstract: An apparatus is provided, comprising: a first circuitry configured to generate a signal at a voltage level for one or more components; a second circuitry configured to generate a clock at a frequency level for the one or more components; a third circuitry configured to intermittently measure a current level of the signal; a fourth circuitry configured to estimate a first average of the current level of the signal over a first time-window; and a fifth circuitry configured to, in response to the first average being higher than a threshold average current, facilitate regulating one or both the voltage level of the signal or the frequency level of the clock.
    Type: Application
    Filed: December 16, 2016
    Publication date: June 21, 2018
    Applicant: Intel Corporation
    Inventors: Alexander Gendler, Boris Mishori, Krishnakanth V. Sistla, Ankush Varma, Avinash N. Ananthakrishnan, Lev Makovsky, Michael Zelikson, Eran Altshuler, Israel Stolero
  • Patent number: 9966940
    Abstract: A power-gate circuit includes a power-gate transistor operable to switch to decouple a first supply voltage from a second supply voltage during an idle mode, and to couple the first supply voltage to the second supply voltage during a full operational mode. Part of the charge stored at a gate terminal of the power-gate transistor, would have been otherwise flushed to ground while turning on the power-gate transistor, is routed to the rail of the second supply voltage of the logic block. Part of the charge on the rail of the second supply voltage is used to charge the gate terminal of the power-gate transistor to deactivate the power-gate transistor if the logic block goes to the idle mode. Energy is saved both ways because of the charge recycling and the ability to use the power gate circuit even in cases where the duration of the idle mode may be short.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: May 8, 2018
    Assignee: INTEL CORPORATION
    Inventors: Shai Rotem, Norbert Unger, Michael Zelikson
  • Patent number: 9594412
    Abstract: In one embodiment, the present invention includes an apparatus having an estimation logic to estimate a dynamic capacitance of a processor circuit of a processor during a plurality of processor cycles, a power gate calculator to calculate a control value for a power gate circuit coupled to a load line and between a voltage regulator and the processor circuit based on the dynamic capacitance estimate, and a controller to control an impedance of the power gate circuit based on the control value. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: March 14, 2017
    Assignee: Intel Corporation
    Inventors: Vjekoslav Svilan, Michael Zelikson, Kelvin Kwan, Naveen Neelakantam, Norbert Unger
  • Publication number: 20170031419
    Abstract: Described herein is an integrated circuit which comprises: a switching voltage regulator (SVR), having one or more bridge drivers, to provide regulated power supply to a plurality of power domains; and a power control unit (PCU) operable to adjust switching frequencies of the SVR according to states of the plurality of power domains, wherein drive strength or active phase count of the one or more bridge drivers is also adjusted by a logic unit of the SVR when the switching frequencies of the SVR are adjusted.
    Type: Application
    Filed: October 11, 2016
    Publication date: February 2, 2017
    Inventors: Gregory Sizikov, Michael Zelikson, Efraim Rotem, Eyal Fayneh
  • Patent number: 9477291
    Abstract: Described herein is an integrated circuit which comprises: a switching voltage regulator (SVR), having one or more bridge drivers, to provide regulated power supply to a plurality of power domains; and a power control unit (PCU) operable to adjust switching frequencies of the SVR according to states of the plurality of power domains, wherein drive strength or active phase count of the one or more bridge drivers is also adjusted by a logic unit of the SVR when the switching frequencies of the SVR are adjusted.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: October 25, 2016
    Assignee: Intel Corporation
    Inventors: Gregory Sizikov, Michael Zelikson, Efraim Rotem, Eyal Fayneh
  • Publication number: 20160202714
    Abstract: Described is an apparatus which comprises: a first power supply node to supply input power supply; a power transistor coupled to the first power supply node; a multiplexer to selectively control gate terminal of the power transistor according to whether the power transistor is to operate as part of a low dropout voltage regulator (LDO-VR) or is to operate as a digital switch; and a second power supply node coupled to the power transistor, the second power supply node to provide power supply to a load from the power transistor.
    Type: Application
    Filed: September 26, 2013
    Publication date: July 14, 2016
    Inventors: Kosta LURIA, Alexander LYAKHOV, Joseph SHOR, Michael ZELIKSON
  • Patent number: 9092210
    Abstract: In one embodiment, a processor includes a core with a front end unit, at least one execution unit, and a back end unit. Multiple voltage drop detectors can be located within the core each to output a voltage drop signal when a detected voltage falls below a threshold voltage. In turn, a current transient logic coupled to receive the voltage drop signals can control a micro-architectural parameter of at least one of the front end unit, execution unit and back end unit responsive to receipt of a voltage drop signal. Other embodiments are described and claimed.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: July 28, 2015
    Assignee: Intel Corporation
    Inventors: Efraim Rotem, Nir Rosenzweig, Doron Rajwan, Nadav Shulman, Alon Naveh, Eliezer Weissmann, Michael Zelikson
  • Publication number: 20150169025
    Abstract: Described herein is an integrated circuit which comprises: a switching voltage regulator (SVR), having one or more bridge drivers, to provide regulated power supply to a plurality of power domains; and a power control unit (PCU) operable to adjust switching frequencies of the SVR according to states of the plurality of power domains, wherein drive strength or active phase count of the one or more bridge drivers is also adjusted by a logic unit of the SVR when the switching frequencies of the SVR are adjusted.
    Type: Application
    Filed: February 27, 2015
    Publication date: June 18, 2015
    Inventors: Gregory Sizikov, Michael Zelikson, Efraim Rotem, Eyal Fayneh
  • Publication number: 20150149794
    Abstract: Methods and systems to adjust a resistance between a supply grid and a power-gated grid during an active state of a power-gated circuitry in response to load changes in the circuitry to maintain a relatively consistent IR droop. Subsets of power gates (PGs) may be selectively enabled and disabled based on changes in a load factor, such as a voltage, which may be monitored at a gated power distribution grid and/or proximate to a transistor gate within the power-gated circuitry. The adjusting may be performed to minimize a difference between the monitored voltage and a reference, such as with successive approximation or CMS software. PG subsets may be distributed within one or more layers of an integrated circuit (IC) die and may be selectively enabled/disabled based on location. PGs may be embedded within lower layers of an integrated circuit (IC) die, such as within metal layers of the IC die.
    Type: Application
    Filed: December 27, 2011
    Publication date: May 28, 2015
    Applicant: Intel Corporation
    Inventors: Michael Zelikson, Vjekoslav Svilan, Norbert Unger, Shai Rotem