Abstract: A tool for analog and mixed signal circuits includes a unit enabling a user to identify one or more critical interconnect lines in a chip architecture and one or more selectable, predefined topologies for said critical interconnect lines. Each topology includes one or more signal wires and a current return path. A majority of the electric field lines are contained within the boundary of the topology. The invention also includes a method for designing analog and mixed signal (AMS) integrated circuits (IC), including defining a chip architecture and a floor plan, identifying one or more critical interconnect lines and selecting pre-designed transmission line topologies for the critical interconnect lines.

Abstract: In some embodiments of the invention, a processor with a power management scheme using dynamically switchable embedded power gates.

Abstract: With embodiments disclosed herein, the distribution of gated power is done using on-die layers without having to come back out and use package layers.

Abstract: An integrated circuit design kit including one or more circuit components topologies, and one or more critical interconnect lines topologies. The interconnect line topologies may be predefined. The kit may further include one or more circuit components models and one or more critical interconnect lines models.

Abstract: A differential cascode amplifier has first and second cascode circuits, driven by two differential signal sources including input resistances. The first cascode circuit includes a first input transistor having a first collector, a first emitter, and a first base, and a first output transistor having a second collector, a second base, and a second emitter coupled to the first collector. The second cascode circuit includes a second input transistor having a third collector, a third emitter, and a third base, and a second output transistor having a fourth collector, a fourth base, and a fourth emitter coupled to the third collector. The amplifier has a first connection connecting the first base to the fourth base, and a second connection connecting the second base to the third base. This cross-connected differential cascode architecture provides doubled output bandwidth and current gain (in dB), further increasing input impedance and output swing.

Abstract: In a system 10 for designing an integrated circuit, a preliminary design of the integrated circuit is defined and critical interconnect lines in the preliminary design are identified. Further, any critical interconnect lines which are affected by crossing lines in the preliminary design are identified, and a transmission line model 35 is defined to represent each critical interconnect line. A layout design of the integrated circuit, comprising circuit components and parameters thereof, is then defined using the preliminary design and the transmission line model 35 for each critical interconnect line. Component parameters are then extracted from the layout design for simulation of the design using the extracted component parameters. During this design process, for each transmission line model 35 representing a critical interconnect line affected by a crossing line, an environment terminal 36 is provided.

Abstract: A differential cascode amplifier has first and second cascode circuits, driven by two differential signal sources including input resistances. The first cascode circuit includes a first input transistor having a first collector, a first emitter, and a first base, and a first output transistor having a second collector, a second base, and a second emitter coupled to the first collector. The second cascode circuit includes a second input transistor having a third collector, a third emitter, and a third base, and a second output transistor having a fourth collector, a fourth base, and a fourth emitter coupled to the third collector. The amplifier has a first connection connecting the first base to the fourth base, and a second connection connecting the second base to the third base. This cross-connected differential cascode architecture provides doubled output bandwidth and current gain (in dB), further increasing input impedance and output swing.

Abstract: In a system 10 for designing an integrated circuit, a preliminary design of the integrated circuit is defined and critical interconnect lines in the preliminary design are identified. Further, any critical interconnect lines which are affected by crossing lines in the preliminary design are identified, and a transmission line model 35 is defined to represent each critical interconnect line. A layout design of the integrated circuit, comprising circuit components and parameters thereof, is then defined using the preliminary design and the transmission line model 35 for each critical interconnect line. Component parameters are then extracted from the layout design for simulation of the design using the extracted component parameters. During this design process, for each transmission line model 35 representing a critical interconnect line affected by a crossing line, an environment terminal 36 is provided.

Abstract: A method for converting a signal from analog-to-digital domain. Upon receipt of an ith with triggering signal, where 1≦i≦N, the method includes initiating at least a partial AD operation. Upon completion of the at least partial operation, the method may includes generating and transmitting an ith+1 triggering signal. The ith+1 triggering signal may be adapted to initiate an ith+1 at least partial operation, thereby creating an asynchronous process. The method further includes repeating the above operations until completion of the analog to digital conversion. In some embodiments of the present invention, upon completion of the conversion, i=N and the ith+1 operation is a power-down function.

Abstract: A method for converting a signal from analog-to-digital domain. Upon receipt of an ith triggering signal, where 1≦i≦N, the method includes initiating at least a partial AD operation. Upon completion of the at least partial operation, the method may includes generating and transmitting an ith+1 triggering signal. The ith+1 triggering signal may be adapted to initiate an ith+1 at least partial operation, thereby creating an asynchronous process. The method further includes repeating the above operations until completion of the analog to digital conversion. In some embodiments of the present invention, upon completion of the conversion, i=N and the ith+1 operation is a power-down function.

Abstract: An integrated circuit design kit including one or more circuit components topologies, and one or more critical interconnect lines topologies. The interconnect line topologies may be predefined. The kit may further include one or more circuit components models and one or more critical interconnect lines models.

Abstract: A differential linear amplifier includes a main differential amplification circuit, coupled to receive a differential input signal at the input of the amplifier and to generate a differential output signal at the output of the amplifier. Odd- and even-order compensation circuits respectively sample odd- and even-order harmonic currents in the main differential amplification circuit and amplify the sampled currents so as to generate odd- and even-order compensation signals for subtraction from the differential output signal. A filter provides phase matching of second- and third-order harmonic components at a desired frequency at the output of the amplifier between the differential output signal and the even- and odd-order compensation signals.

Abstract: Instrumentation driver apparatus, including a main driver, coupled to receive an alternating input signal and having a main circuit structure, which is adapted to generate, in response to the alternating input signal, a main output signal with alternating voltage. The apparatus includes a mirror driver, coupled to receive a direct voltage input and having a mirror circuit structure located in proximity to the main circuit structure, which is adapted to generate a mirror output signal in response to the direct voltage input, such that a variation in an operating condition of the main driver causes a corresponding variation in the mirror output signal. The apparatus further includes a feedback circuit, coupled to receive the mirror output signal, which provides in response to the mirror output signal a feedback stabilization input to the main driver so as to stabilize the main output signal.

Abstract: An integrated circuit device, including a substrate and a signal source disposed on the substrate. The signal. source is adapted to supply a pair of signals to a first plulrality of customers positioned remote from the signal source on the substrate, each of which customers is adapted to receive the pair of signals. There are a second plurality of conductors, formed substantially within a single layer of conductive material deposited on the substrate, and arranged to distribute the pair of signals from the signal source to each of the customers.

Abstract: A differential linear amplifier includes a main differential amplification circuit, coupled to receive a differential input signal at the input of the amplifier and to generate a differential output signal at the output of the amplifier. Odd- and even-order compensation circuits respectively sample odd- and even-order harmonic currents in the main differential amplification circuit and amplify the sampled currents so as to generate odd- and even-order compensation signals for subtraction from the differential output signal. A filter provides phase matching of second- and third-order harmonic components at a desired frequency at the output of the amplifier between the differential output signal and the even- and odd-order compensation signals.

Abstract: A variable output voltage swing differential driver including an open-loop current control unit operative to produce a control current, and a voltage output unit receiving the control current and operative to produce a voltage output having a variable output swing.