Abstract: A delay locked-loop circuit includes: a phase comparator detecting a phase difference between an external clock and an internal clock; an up/down counter controlling a delay time in accordance with an output signal from the phase comparator; and a delay line including plural unit delay circuits corresponding to plural bits of a signal output from the up/down counter in order to control the delay of the external clock to conform the external clock to the internal clock, and in which the unit delay circuits controlled by the output from a same bit in the output from the up/down counter are not connected adjacently to each other in the connection of the plural unit delay circuits in series.

Abstract: A flip-flop circuit includes: a first latch circuit that receives input of a data signal and a rise delay clock signal, raises a signal of a first node according to the fall of the rise delay clock signal, and lowers the signal of the first node according to the rise of the rise delay clock signal; a second latch circuit that receives input of the signal of the first node and the clock signal and lowers a signal of a second node at timing when the clock signal falls; a third latch circuit that receives input of the signal of the second node and the clock signal and generates an output signal for maintaining the data signal; and a pull-down circuit that pulls down the signal of the first node with the rise delay clock signal.

Abstract: A delay synchronization loop type clock signal generating circuit includes: a digital delay line for delaying a first clock signal and generating a second clock signal; a ring-type shift register for setting the delay time length of the digital delay line by flip-flop output of each stage thereof; and a delay amount control unit for controlling supply of shift clocks to the ring-type shift register, based on phase relation between the first clock signal and the second clock signal.

Abstract: A delay synchronization loop type clock signal generating circuit includes: a delay line for delaying a first clock signal by a set delay amount and outputting; a delay time length setting unit for setting a delay time length of the delay line, based on phase difference between a second clock signal output from an output terminal and the first clock signal; a phase relation determining unit for determining whether or not the phase relation of the first clock signal and the second clock signal are in a particular phase relation; and a phase inversion/non-inversion unit for performing phase inversion of the first clock signal on a transmission path including the delay line, at the time of detecting the particular phase relation.

Abstract: A liquid crystal display (“LCD”) includes a first voltage shift circuit at a front stage of an inverter circuit. The first voltage shift circuit includes a second transistor having a source serving as an input, and a gate and drain connected to each other, and is operated as a diode, and a first transistor having a source connected to a power supply, a gate connected to a ground, and a drain connected to the drain of the second transistor. An input signal shifts voltage by a threshold of the second transistor, and then is input into the inverter circuit. Further, a first condenser is inserted between an input node and the gate of the second transistor. Therefore, the LCD has a level shift circuit with a small circuit area and a rapid response speed.

Abstract: A clock signal generation circuit of a delay locked loop type includes a delay line configured to delay a first clock signal to generate a second clock signal; a delay amount controller configured to change the amount of delay in the delay line in such a manner that a phase of the second clock signal is in synchronization with a phase of the first clock signal; a pseudo-lock detection section configured to detect a pseudo-locked state of the first clock signal and the second clock signal; and a pseudo-locked state release section configured to change the amount of delay in the delay line in a case that the pseudo-locked state is detected.

Abstract: A liquid crystal display includes a pixel group including a first pixel having a first thin film transistor and a second pixel having a second thin film transistor. A gate line provides a driving signal to a gate of the first and second thin film transistors. A first storage capacitor line is arranged substantially parallel with the gate line and adjacent to one side of the first pixel. A second storage capacitor line is arranged substantially parallel with the gate line and adjacent to an opposite side of the first pixel. The liquid crystal display includes a first storage capacitor arranged in the first pixel and connected between the first thin film transistor and the first storage capacitor line. A second storage capacitor is arranged in the second pixel and is connected between the second thin film transistor and the second storage capacitor line.

Abstract: A level shift circuit basically has a configuration connecting two CMOS inverter circuits in parallel, furnishes an input signal to a control terminal of the inverter circuit, obtains an output signal from an output terminal of the inverter circuit, and has a function for level shifting the voltage amplitude of the input signal to the voltage amplitude of the supply voltage of the inverter circuit. The signal that is input by the gate terminal of an n-channel transistor arranged in each of two current paths forming the level shift circuit is not a direct input signal but a signal that is supplied by adding an offset corresponding to the threshold of each n-channel transistor with respect to the voltage amplitude of the input signal via the input voltage converter circuit.

Abstract: In the active matrix display device with a DRAM as the retaining circuit, the voltage retained in the retaining circuit is set in the brightness saturation region, which is outside the region of the voltage used in the moving picture display mode. With the voltage in this region, the difference in the brightness will not be recognized even if the voltage decreases before the refreshing operation. This prevents flickering and improves the display quality.

Abstract: A liquid crystal display includes a plurality of gate lines having odd-numbered gate lines and even-numbered gate lines, a plurality of source lines, a first gate driver which drives the odd-numbered gate lines, a second gate driver which drives the even-numbered gate lines and a driving controller which outputs an overdriven image signal in at least one driving period of a plurality of driving periods and outputs a normal image signal in remaining driving periods of the plurality of driving periods. The overdriven image signal is obtained by adding an overdrive voltage to the normal image signal, and the overdrive voltage is set according to a level of the normal image signal.

Abstract: A display capable of suppressing reduction of a scanning property is provided. This display comprises a shift register circuit formed by connecting a plurality of first circuit parts each including a first conductivity type first transistor connected to a first potential and turned on in response to a clock signal, a first conductivity type second transistor connected to a second potential and a first conductivity type third transistor, connected between the gate of the first transistor and the second potential, having two gate electrodes electrically connected with each other.

Abstract: A display capable of correctly displaying images with brightness in response to a video signal is provided. This display comprises a pixel including a p-type first field-effect transistor subjected to application of a first bias voltage in the period of an operation of holding a pixel potential and a pixel electrode. The display applies a second bias voltage larger than the first bias voltage to the p-type first field-effect transistor in a prescribed period other than the period for the operation of holding the pixel potential.

Abstract: The non-linear amplifier performs a gamma correction to the analog video signal inputted from outside along with the non-linear correction for eliminating the effect of the dependency of the dielectric constant of the liquid crystal on the pixel potential Vp. The analog video signal corrected by the non-linear amplifier is then applied to a pair of amplifiers and that output a pair of signals with the polarity inverted against the potential Vcom of the common electrode. A switching circuit switches and outputs the output from the pair of the amplifiers according to the inverted signal.

Abstract: A small or middle-sized liquid crystal display employing a black insertion driving method overcomes the after-image or blurring of a moving picture by shifting the level of a voltage applied to a storage capacitor line within a predetermined period corresponding to about 20% to about 80% that lasts after image signals are applied to pixels until the next image signals are applied to the pixels by using two types of voltages that shift pixel voltages into a black display potential.

Abstract: A liquid crystal display having an improved pixel aperture ratio includes vertical scan lines disposed between adjacent pixels, video signal lines disposed between adjacent pixels, and sub-capacitor lines disposed between adjacent pixels while regularly and repeatedly crossing the vertical scan lines.

Abstract: A display allowing further miniaturization when including a plurality of display panels is obtained. This display comprises a first display panel formed on a substrate and a second display panel formed on the same substrate on a region different from that formed with the first display panel. Thus, the display can be further miniaturized as compared with that having a first display panel and a second display panel formed on different substrates.

Abstract: A voltage boosting circuit performs variable frequency control that gradually increases frequencies of clock signals from a low frequency to a high frequency during a boosting operation period for which a low output voltage of a DC-DC converter when the power is turned on is boosted up to a predetermined voltage. Thus, the frequencies of clock signals may be set according to the boosting operation of the DC-DC converter. Consequently, the operation of the DC-DC converter may be stabilized until the stable operation period is performed after the DC-DC converter starts to operate.

Abstract: A DC/DC converter of a liquid crystal display includes a charge pump having a thin film transistor, a capacitor and a diode. The thin film transistor is formed on an insulating substrate. A first main electrode of the thin film transistor is connected to an output terminal and a control electrode of the thin film transistor receives a control signal. The thin film transistor includes a non-monocrystal semiconductor. The capacitor has a first electrode connected to a second main electrode of the thin film transistor and a second electrode receiving a variable voltage. The diode is electrically connected between the second main electrode of the thin film transistor, the first electrode of the capacitor, and a power terminal in series. The diode includes a mono-crystal semiconductor.

Abstract: A liquid crystal display includes a plurality of pixels, each of which includes a thin film transistor (TFT), a gate line supplying a driving signal to a gate of the TFT of each pixel, a liquid crystal capacitor included in each pixel and connected to one terminal of the TFT in a corresponding pixel, a sub-capacitor line aligned in parallel to the gate line, a sub-capacitor included in each pixel and connected between one terminal of the TFT in a corresponding pixel and the sub-capacitor line, and a driving circuit having at least four voltages, selecting one of the voltages and supplying the selected voltage to the sub-capacitor line to drive the liquid crystal display in a state in which the liquid crystal capacitor is capacitively coupled to the sub-capacitor.

Abstract: There is provided a display having a shift register circuit which can prevent an increase in power consumption. The display is provide with a shift register circuit including a first circuit part comprising a fourth transistor turned on in response to a first signal to supply a clock signal to a first transistor, and a second circuit part comprising an eighth transistor turned on in response to a second signal by which a period of on state which does not overlap with a period of on state of the fourth transistor can be obtained, to supply the clock signal to a fifth transistor.