Abstract: When a switching TFT is switched on, a data voltage on a data line is stored in a storage capacitor as a gate voltage of a driver TFT. In this state, a voltage on a pulse drive line is caused to fall. AMOS type capacity element having a second electrode connected to a reference voltage is connected to a gate of the driver TFT. The MOS type capacity element is in an ON state before a fall of the pulse drive line and becomes an OFF state during the fall, and a capacitance changes at the switching of ON state to the OFF state. Therefore, the slope of fall of the gate voltage changes, and the gate voltage after the fall on the pulse drive line can be corrected corresponding to the variation in the threshold values among driver TFTs.

Abstract: In a liquid crystal display device includes; a plurality of pixels arranged substantially in a matrix pattern; wherein each of the plurality of pixel includes; first and second thin film transistors including current paths connected to a source line in series, a storage capacitor line, a first capacitor connected between the first and second thin film transistors and connected to the storage capacitor line, a second capacitor connected between one of the source and the drain of the second thin film transistor and a pixel electrode and connected to the storage capacitor line, and a third capacitor including the pixel electrode, a common electrode, and a liquid crystal between the pixel electrode and the common electrode, wherein an overdrive voltage Vover satisfying equation Vover = C ? ? ? 1 C ? ? ? 2 + C ? ? ? lc · Vsig is added to a display signal voltage Vsig and a resultant voltage is applied to the source line.

Abstract: A liquid crystal display (“LCD”) includes a first voltage shift circuit at a front stage of an inverter circuit. The first voltage shift circuit includes a second transistor having a source serving as an input, and a gate and drain connected to each other, and is operated as a diode, and a first transistor having a source connected to a power supply, a gate connected to a ground, and a drain connected to the drain of the second transistor. An input signal shifts voltage by a threshold of the second transistor, and then is input into the inverter circuit. Further, a first condenser is inserted between an input node and the gate of the second transistor. Therefore, the LCD has a level shift circuit with a small circuit area and a rapid response speed.

Abstract: A level shift circuit basically has a configuration connecting two CMOS inverter circuits in parallel, furnishes an input signal to a control terminal of the inverter circuit, obtains an output signal from an output terminal of the inverter circuit, and has a function for level shifting the voltage amplitude of the input signal to the voltage amplitude of the supply voltage of the inverter circuit. The signal that is input by the gate terminal of an n-channel transistor arranged in each of two current paths forming the level shift circuit is not a direct input signal but a signal that is supplied by adding an offset corresponding to the threshold of each n-channel transistor with respect to the voltage amplitude of the input signal via the input voltage converter circuit.

Abstract: A current generating circuit, which generates a driving current weighed corresponding to a digital image signal, is disposed for each pixel in the display device of this invention. The driving current is supplied to an organic El element. The current generating circuit has D/A conversion function, which is capable of converting the digital image signal into the weighed driving current, enabling the gradation display corresponding to the digital image signal.

Abstract: In a buffer amplifier which receives an input signal on a positive input terminal, has an output terminal connected to a negative input terminal, and outputs a stabilized output signal, a switch for connecting the positive input terminal and the output terminal is provided. By switching the switch ON, the output of the buffer amplifier is set close to the input.

Abstract: A first switch which controls input of an input signal to an input terminal of a buffer amplifier is provided. A first capacitor having a first terminal connected to an input terminal of the buffer amplifier and a second terminal connected to an output terminal of the buffer amplifier via a second switch is provided and a third switch which switches supply of the input signal to the second terminal of the first capacitor ON and OFF is provided. The first switch and the second switch are switched ON and the third switch is switched OFF so that the first capacitor is charged with a potential difference between the input signal and the output signal. Then, the first switch and the second switch are switched OFF, the third switch is switched ON, and the input signal is supplied to the second terminal of the first capacitor so that a voltage derived by adding a difference between the input signal and the output signal to the input signal is supplied to the input terminal of the buffer amplifier.

Abstract: A digital image signal fed from the drain signal line is written into a retaining circuit through a pixel element selection TFT and a liquid crystal displays an image based on the digital image signal. In the retaining circuit, a threshold voltage of the first inverter circuit is set smaller than a threshold voltage of the second inverter circuit. Therefore, false writing of the image signal data into the retaining circuit can be prevented, leading to an accurate display the image signal retained in the retaining circuit.

Abstract: A digital image signal is serially transferred to each of pixels through a drain signal line. The digital image signal is sampled at pixel selecting transistors, converted from a serial signal to a parallel signal, and then converted to an analog image signal by a DA converter. This DA converter includes a plurality of capacitor electrodes coupled to a pixel electrode at a weighted capacitance ratio and a clock supplying portion for supplying periodic clock signals to the plurality of the capacitor electrodes in response to the digital image signal. The analog image signal is applied to the pixel electrode. This simplifies a configuration of peripheral circuits of the pixel, and accordingly reduces the frame area of a panel and the number of wiring lines.

Abstract: A display device capable of analog and digital image display has a retaining circuit holding an image signal disposed for each of the pixel elements. In the memory operation mode, an output from an oscillation unit formed inside the display panel is supplied to the pixel element electrodes of the display. The on-resistance of an output transistor for the pixel electrode is higher than the on-resistance of thin film transistors of the inverters in the oscillation unit. In the memory operation mode, gate and drain lines are set at predetermined voltages and an output of a voltage booster circuit formed in the display panel is used as a reference voltage of the retaining circuit and used for switching a selection circuit selecting image display circuits.

Abstract: A display capable of inhibiting a logic composition circuit from outputting a signal to a gate line or a drain line at unintentional timing is obtained. In this display, at least either a first shift register circuit portion or a second shift register circuit portion includes a reset transistor for resetting the voltage supply source of a node outputting a first shift signal or a second shift signal to a second voltage supply source not turning on transistors of a logic composition circuit portion in response to an output signal received from a shift register circuit portion precedent thereto by at least two stages with respect to a scanning direction.

Abstract: In a display device, clock supplying transistors turn on and off in response to a digital image signal retained in capacitance elements fed from drain signal lines through pixel element selection transistors. The image signal is applied to capacitance electrodes through the clock supplying transistors. Voltages change at the pixel element electrodes according to the value of the digital image signal. Therefore, a DA conversion is possible at the pixel element portion, leading to simplification of the peripheral circuit configuration around pixel element portions and the reduction of the framing area of the panel.

Abstract: A display capable of inhibiting a logic composition circuit from outputting a signal to a gate line or a drain line at unintentional timing is obtained. This display comprises a shift register circuit including a logic composition circuit portion constituted of a plurality of first conductive type transistors turned on with a first voltage supply source for receiving a first shift signal and a second shift signal and outputting a shift output signal by logically compositing the first shift signal and the second shift signal with each other. At least either a first shift register circuit portion or a second shift register circuit portion includes a reset transistor for resetting the voltage supply source of a node outputting the first shift signal or the second shift signal to a second voltage supply source not turning on the transistors of the logic composition circuit portion in response to a prescribed drive signal.

Abstract: A driving circuit of an LCD display apparatus, which adjusts the sampling timing of a video signal. Driving signals from a driving IC and a reference power source are supplied via a flexible printed circuit FPC to an LCD panel. A horizontal clock signal is subjected to switching adjustment in a propagation delay adjustment circuit, which alternatively switches a delay amount of the horizontal clock signal between two levels, and the resulting horizontal clock signal subjected to the switching adjustment is then supplied to a horizontal shift register. The FPC generates a switching signal by branching from either a high potential voltage signal VDD or a low potential voltage signal VSS and supplies the switching signal to the propagation delay adjustment circuit. A phase switching circuit having a function similar to that of the propagation delay adjustment circuit may be provided within the driving IC.

Abstract: A display having a shift register circuit capable of suppressing increase of power consumption is provided. This display comprises a shift register circuit including a shift register circuit portion including a first circuit portion having a second transistor turned on in response to a first signal and a second circuit portion having a sixth transistor turned on in response to a second signal providing an ON-state period not overlapping with an ON-state period of the second transistor and an input signal switching circuit portion for switching the first and second signals supplied to the second and sixth transistors respectively.

Abstract: An LCD device driven with storage capacitors prevents defective image display caused by capacitive coupling between data lines and storage capacitor lines. The LCD device includes pixel electrodes arranged at intersections between drain lines and gate lines, switching elements, storage capacitor lines corresponding to the gate lines, storage capacitors having first electrodes connected to the pixel electrodes and second electrodes connected to the storage capacitor lines, a switching circuit for selectively applying a potential to the storage capacitor lines, and a drain driver. The drain driver selects some of the data lines so that an equal number of image data signals having a positive polarity and image data signals having a negative polarity are provided to the selected data lines and simultaneously provides the selected data lines with the image data signals having a positive polarity and the image data signals having a negative polarity.

Abstract: A display capable of rendering flickering hard to visually recognize and reducing power consumption is obtained. This display comprises first and second pixel portions including subsidiary capacitors having first electrodes connected to pixel electrodes and second electrodes respectively, first and second subsidiary capacitance lines connected to the second electrodes of the first and second pixel portions respectively and a signal supply circuit supplying first and second signals having first and second voltages to the first and second subsidiary capacitance lines respectively.

Abstract: In the active matrix display device with a DRAM as the retaining circuit, the voltage retained in the retaining circuit is set in the brightness saturation region, which is outside the region of the voltage used in the moving picture display mode. With the voltage in this region, the difference in the brightness will not be recognized even if the voltage decreases before the refreshing operation. This prevents flickering and improves the display quality.

Abstract: The level of a storage capacitor line is changed between two types, an H level and an L level. As a result of this change, the voltage applied to a liquid crystal is shifted so that a sufficient voltage is applied to the liquid crystal to perform a display operation. Then, at least one of two voltage levels of the storage capacitor line is used in common with the potential of at least one of plurality of voltage levels which are used in vertical driver which drives the said selection line. Furthermore, the values of the storage capacitance and parasitic capacitance for the storage capacitor line are set within a specific range.

Abstract: The level of a storage capacitor line changes between two types, an H level and an L level. As a result of this change, the voltage applied to a liquid crystal is shifted so that a sufficient voltage is applied to the liquid crystal to perform a display operation. Then, by changing the voltage value of the difference between a first level and a second level, the contrast and screen brightness are adjusted. Furthermore, the capacitances generated at the locations where the two storage capacitor lines and the data line intersect are set to be substantially the same.