Abstract: In the active matrix display device with a DRAM as the retaining circuit, the voltage retained in the retaining circuit is set in the brightness saturation region, which is outside the region of the voltage used in the moving picture display mode. With the voltage in this region, the difference in the brightness will not be recognized even if the voltage decreases before the refreshing operation. This prevents flickering and improves the display quality.

Abstract: A display device capable of analog and digital image display has a retaining circuit holding an image signal disposed for each of the pixel elements. In the memory operation mode, an output from an oscillation unit formed inside the display panel is supplied to the pixel element electrodes of the display. The on-resistance of an output transistor for the pixel electrode is higher than the on-resistance of thin film transistors of the inverters in the oscillation unit. In the memory operation mode, gate and drain lines are set at predetermined voltages and an output of a voltage booster circuit formed in the display panel is used as a reference voltage of the retaining circuit and used for switching a selection circuit selecting image display circuits.

Abstract: The non-linear amplifier performs a gamma correction to the analog video signal inputted from outside along with the non-linear correction for eliminating the effect of the dependency of the dielectric constant of the liquid crystal on the pixel potential Vp. The analog video signal corrected by the non-linear amplifier is then applied to a pair of amplifiers and that output a pair of signals with the polarity inverted against the potential Vcom of the common electrode. A switching circuit switches and outputs the output from the pair of the amplifiers according to the inverted signal.

Abstract: A delay circuit capable of suppressing reduction of the yield in manufacturing is provided. This delay circuit comprises an inverter circuit having a prescribed logical threshold voltage and a first transistor connected in parallel to the inverter circuit. The first transistor is turned on when an input signal in and an output signal from the inverter circuit are at a first voltage and a second voltage respectively and further turned on for at least a partial period in a period when the input signal in the inverter circuit reaches a voltage corresponding to the logical threshold voltage of the inverter circuit from the first voltage for changing from the first voltage to the second voltage thereby functioning substantially as a capacitor.

Abstract: The present invention provides a display capable of suppressing increase of consumed electric current. The display includes a first conductive type first transistor whose source or drain is connected to a signal line provided with a signal switched between a first voltage and a second voltage, the first transistor being ON in response to a clock signal provided, and the source or drain of the first transistor being provided with a signal of the first voltage from the signal line during at least a period where the first transistor is ON in response to the clock signal, a first conductive type second transistor connected to the first voltage supply source side, and a first conductive type third transistor connected between the gate of the first transistor and the first voltage supply source to bring the first transistor to OFF state when the second transistor is in ON state.

Abstract: Within one pixel element 200, two display circuits corresponding to the analog display mode and the digital display mode are disposed such that they are adjacent to each other. One of these two display circuits can be selected through the circuit selection circuits 40 or 43. Since the high voltage power line 150 of the retaining circuit 110, which is used under the digital display mode, also performs as the signal selection line 88, it is possible to have the high density integration of the pixel element 200. Also, the bias voltage Vsc supplied through the selection storage capacitor line 81 is same as the signal A. Therefore, the storage capacitor line 81 is connected to the drain of the TFT 122 of the signal selection circuit 120 so that the signal line 82 for supplying the signal A can be omitted. Thus, the high-density integration of the pixel element 200 can be achieved.

Abstract: When a switching TFT is switched on, a data voltage on a data line is stored in a storage capacitor as a gate voltage of a driver TFT. In this state, a voltage on a pulse drive line is caused to fall. AMOS type capacity element having a second electrode connected to a reference voltage is connected to a gate of the driver TFT. The MOS type capacity element is in an ON state before a fall of the pulse drive line and becomes an OFF state during the fall, and a capacitance changes at the switching of ON state to the OFF state. Therefore, the slope of fall of the gate voltage changes, and the gate voltage after the fall on the pulse drive line can be corrected corresponding to the variation in the threshold values among driver TFTs.

Abstract: There is provided a display having a shift register circuit which can prevent an increase in power consumption. The display is provide with a shift register circuit including a first circuit part comprising a fourth transistor turned on in response to a first signal to supply a clock signal to a first transistor, and a second circuit part comprising an eighth transistor turned on in response to a second signal by which a period of on state which does not overlap with a period of on state of the fourth transistor can be obtained, to supply the clock signal to a fifth transistor.

Abstract: There is provided a display which can prevent image deterioration. The display is provide with a shift register circuit including a first circuit part comprising a first transistor of first conductivity type connected to a first potential side and turned on in response to a clock signal, a second transistor of first conductivity type connected to a second potential side, a third transistor of first conductivity type connected between a gate of the first transistor and the second potential and a high resistance connected between the gate of the first transistor and a clock signal line.

Abstract: A display capable of correctly displaying images with brightness in response to a video signal is provided. This display comprises a pixel including a p-type first field-effect transistor subjected to application of a first bias voltage in the period of an operation of holding a pixel potential and a pixel electrode. The display applies a second bias voltage larger than the first bias voltage to the p-type first field-effect transistor in a prescribed period other than the period for the operation of holding the pixel potential.

Abstract: A display capable of suppressing reduction of a scanning property is provided. This display comprises a shift register circuit formed by connecting a plurality of first circuit parts each including a first conductivity type first transistor connected to a first potential and turned on in response to a clock signal, a first conductivity type second transistor connected to a second potential and a first conductivity type third transistor, connected between the gate of the first transistor and the second potential, having two gate electrodes electrically connected with each other.

Abstract: A digital image signal is serially transferred to each of pixels through a drain signal line. The digital image signal is sampled at pixel selecting transistors, converted from a serial signal to a parallel signal, and then converted to an analog image signal by a DA converter. This DA converter includes a plurality of capacitor electrodes coupled to a pixel electrode at a weighted capacitance ratio and a clock supplying portion for supplying periodic clock signals to the plurality of the capacitor electrodes in response to the digital image signal. The analog image signal is applied to the pixel electrode. This simplifies a configuration of peripheral circuits of the pixel, and accordingly reduces the frame area of a panel and the number of wiring lines.

Abstract: A display device capable of analog and digital image display has a retaining circuit holding an image signal disposed for each of the pixel elements. In the memory operation mode, an output from an oscillation unit formed inside the display panel is supplied to the pixel element electrodes of the display. The on-resistance of an output transistor for the pixel electrode is higher than the on-resistance of thin film transistors of the inverters in the oscillation unit. In the memory operation mode, gate and drain lines are set at predetermined voltages and an output of a voltage booster circuit formed in the display panel is used as a reference voltage of the retaining circuit and used for switching a selection circuit selecting image display circuits.

Abstract: A current generating circuit, which generates a driving current weighed corresponding to a digital image signal, is disposed for each pixel in the display device of this invention. The driving current is supplied to an organic El element. The current generating circuit has D/A conversion function, which is capable of converting the digital image signal into the weighed driving current, enabling the gradation display corresponding to the digital image signal.

Abstract: A display allowing further miniaturization when including a plurality of display panels is obtained. This display comprises a first display panel formed on a substrate and a second display panel formed on the same substrate on a region different from that formed with the first display panel. Thus, the display can be further miniaturized as compared with that having a first display panel and a second display panel formed on different substrates.

Abstract: A display device capable of analog and digital image display has a retaining circuit holding an image signal disposed for each of the pixel elements. In the memory operation mode, an output from an oscillation unit formed inside the display panel is supplied to the pixel element electrodes of the display. The on-resistance of an output transistor for the pixel electrode is higher than the on-resistance of thin film transistors of the inverters in the oscillation unit. In the memory operation mode, gate and drain lines are set at predetermined voltages and an output of a voltage booster circuit formed in the display panel is used as a reference voltage of the retaining circuit and used for switching a selection circuit selecting image display circuits.

Abstract: In the active matrix display device with a DRAM as the retaining circuit, the voltage retained in the retaining circuit is set in the brightness saturation region, which is outside the region of the voltage used in the moving picture display mode. With the voltage in this region, the difference in the brightness will not be recognized even if the voltage decreases before the refreshing operation. This prevents flickering and improves the display quality.

Abstract: A display device capable of analog and digital image display has a retaining circuit holding an image signal disposed for each of the pixel elements. In the memory operation mode, an output from an oscillation unit formed inside the display panel is supplied to the pixel element electrodes of the display. The on-resistance of an output transistor for the pixel electrode is higher than the on-resistance of thin film transistors of the inverters in the oscillation unit. In the memory operation mode, gate and drain lines are set at predetermined voltages and an output of a voltage booster circuit formed in the display panel is used as a reference voltage of the retaining circuit and used for switching a selection circuit selecting image display circuits.

Abstract: In a display device, clock supplying transistors turn on and off in response to a digital image signal retained in capacitance elements fed from drain signal lines through pixel element selection transistors. The image signal is applied to capacitance electrodes through the clock supplying transistors. Voltages change at the pixel element electrodes according to the value of the digital image signal. Therefore, a DA conversion is possible at the pixel element portion, leading to simplification of the peripheral circuit configuration around pixel element portions and the reduction of the framing area of the panel.

Abstract: A display device capable of analog and digital image display has a retaining circuit holding an image signal disposed for each of the pixel elements. In the memory operation mode, an output from an oscillation unit formed inside the display panel is supplied to the pixel element electrodes of the display. The on-resistance of an output transistor for the pixel electrode is higher than the on-resistance of thin film transistors of the inverters in the oscillation unit. In the memory operation mode, gate and drain lines are set at predetermined voltages and an output of a voltage booster circuit formed in the display panel is used as a reference voltage of the retaining circuit and used for switching a selection circuit selecting image display circuits.