Patents by Inventor Mieno Fumitake
Mieno Fumitake has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9853030Abstract: Various embodiments provide semiconductor devices and methods for forming the same. A first fin and a second fin are formed on a semiconductor substrate. A first dielectric layer is formed on the semiconductor substrate and has a top surface lower than a top surface of both of the first fin and the second fin. A gate structure is formed on the first dielectric layer and covering across a first portion of each of the first fin and the second fin. A second portion of the first fin on both sides of the gate structure is removed, forming a first recess. A first semiconductor layer is formed in the first recess. A second dielectric layer is formed on the first dielectric layer and the first semiconductor layer, and exposes a top surface of the second fin. A second semiconductor layer is formed on the exposed top surface of the second fin.Type: GrantFiled: May 5, 2016Date of Patent: December 26, 2017Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventors: Mieno Fumitake, Jianhua Ju
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Patent number: 9543390Abstract: A transistor includes a semiconductor substrate comprising a first region and a second region. The transistor further includes an emitter and a base disposed on the first region, and a collector disposed on the second region. The emitter includes a heterojunction. The heterojunction is at a same height as a junction between two different insulating materials that separate the emitter and the base.Type: GrantFiled: October 14, 2014Date of Patent: January 10, 2017Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventor: Mieno Fumitake
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Patent number: 9437597Abstract: The present disclosure provides a static memory cell and fabrication method. A first fin part is formed on a semiconductor substrate. An isolation layer is formed to cover a lower portion of sidewalls of the first fin part. A first dummy gate structure is formed across the first fin part. A dielectric layer is formed on the isolation layer. A mask layer is formed on the dielectric layer with a first opening to expose the top surface of the first dummy gate structure. The first dummy gate structure is removed through the first opening to form a first trench exposing the first fin part. A portion of the isolation layer is removed through the first opening to form a second trench exposing a portion of sidewalls of the first fin part below the top surface of the isolation layer. A first gate structure is formed by filling up the first and the second trenches.Type: GrantFiled: February 2, 2016Date of Patent: September 6, 2016Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventor: Mieno Fumitake
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Publication number: 20160247807Abstract: Various embodiments provide semiconductor devices and methods for forming the same. A first fin and a second fin are formed on a semiconductor substrate. A first dielectric layer is formed on the semiconductor substrate and has a top surface lower than a top surface of both of the first fin and the second fin. A gate structure is formed on the first dielectric layer and covering across a first portion of each of the first fin and the second fin. A second portion of the first fin on both sides of the gate structure is removed, forming a first recess. A first semiconductor layer is formed in the first recess. A second dielectric layer is formed on the first dielectric layer and the first semiconductor layer, and exposes a top surface of the second fin. A second semiconductor layer is formed on the exposed top surface of the second fin.Type: ApplicationFiled: May 5, 2016Publication date: August 25, 2016Inventors: MIENO FUMITAKE, JIANHUA JU
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Patent number: 9362286Abstract: Various embodiments provide semiconductor devices and methods for forming the same. A first fin and a second fin are formed on a semiconductor substrate. A first dielectric layer is formed on the semiconductor substrate and has a top surface lower than a top surface of both of the first fin and the second fin. A gate structure is formed on the first dielectric layer and covering across a first portion of each of the first fin and the second fin. A second portion of the first fin on both sides of the gate structure is removed, forming a first recess. A first semiconductor layer is formed in the first recess. A second dielectric layer is formed on the first dielectric layer and the first semiconductor layer, and exposes a top surface of the second fin. A second semiconductor layer is formed on the exposed top surface of the second fin.Type: GrantFiled: December 18, 2014Date of Patent: June 7, 2016Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventors: Mieno Fumitake, Jianhua Ju
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Patent number: 9362331Abstract: A method for forming image sensors includes providing a substrate and forming a plurality of photo diode regions, each of the photo diode regions being spatially disposed on the substrate. The method also includes forming an interlayer dielectric layer overlying the plurality of photo diode regions, forming a shielding layer formed overlying the interlayer dielectric layer, and applying a silicon dioxide bearing material overlying the shielding layer. The method further includes etching portions of the silicon dioxide bearing material to form a plurality of first lens structures, and continuing to form each of the plurality of first lens structures to provide a plurality of finished lens structures.Type: GrantFiled: April 1, 2014Date of Patent: June 7, 2016Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Herb He Huang, Mieno Fumitake
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Publication number: 20160155746Abstract: The present disclosure provides a static memory cell and fabrication method. A first fin part is formed on a semiconductor substrate. An isolation layer is formed to cover a lower portion of sidewalls of the first fin part. A first dummy gate structure is formed across the first fin part. A dielectric layer is formed on the isolation layer. A mask layer is formed on the dielectric layer with a first opening to expose the top surface of the first dummy gate structure. The first dummy gate structure is removed through the first opening to form a first trench exposing the first fin part. A portion of the isolation layer is removed through the first opening to form a second trench exposing a portion of sidewalls of the first fin part below the top surface of the isolation layer. A first gate structure is formed by filling up the first and the second trenches.Type: ApplicationFiled: February 2, 2016Publication date: June 2, 2016Inventor: MIENO FUMITAKE
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Patent number: 9293550Abstract: The present invention discloses a semiconductor device and a method for manufacturing the semiconductor device. The semiconductor device includes a gate insulating layer formed on an inner wall of a substrate recess, a work function material layer formed on the gate insulating layer so as to apply a tensile stress or a compressive stress to a channel of a MOS field-effect transistor, and a gate metal formed on the work function material layer. The method for manufacturing the semiconductor device includes forming a work function material layer on a gate insulating layer so as to apply a tensile stress or a compressive stress to a channel of a MOS field-effect transistor, wherein the gate insulating layer is formed on an inner wall of a substrate recess, and depositing a gate metal on the work function material layer.Type: GrantFiled: July 11, 2013Date of Patent: March 22, 2016Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventor: Mieno Fumitake
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Patent number: 9287387Abstract: The present disclosure provides a static memory cell and fabrication method. A first fin part is formed on a semiconductor substrate. An isolation layer is formed to cover a lower portion of sidewalls of the first fin part. A first dummy gate structure is formed across the first fin part. A dielectric layer is formed on the isolation layer. A mask layer is formed on the dielectric layer with a first opening to expose the top surface of the first dummy gate structure. The first dummy gate structure is removed through the first opening to form a first trench exposing the first fin part. A portion of the isolation layer is removed through the first opening to form a second trench exposing a portion of sidewalls of the first fin part below the top surface of the isolation layer. A first gate structure is formed by filling up the first and the second trenches.Type: GrantFiled: April 15, 2015Date of Patent: March 15, 2016Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventor: Mieno Fumitake
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Patent number: 9190331Abstract: A non-planar JFET device having a thin fin structure is provided. A fin is formed projecting upwardly from or through a top surface of a substrate, where the fin has a first semiconductor layer portion formed from a first semiconductor material of a first conductivity type. The first semiconductor layer portion has a source region and a drain region, a channel region extending between the source region and the drain region. Two or more channel control regions are formed adjoining the channel region for generating charge depletion zones at and extending into the channel region for thereby controlling current conduction through the channel region. A gate is provided so as to adjoin and short together the at least two channel control regions from the outer sides of the channel control regions.Type: GrantFiled: October 2, 2014Date of Patent: November 17, 2015Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventor: Mieno Fumitake
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Patent number: 9190330Abstract: A method of manufacturing a semiconductor device is provided. The method includes providing a fin protruding upwardly from or through a surface of a substrate, forming a to-be-sacrificed dummy gate enwrapping a first portion of the fin, forming a first insulating material layer so as to at least cover an exposed second portion of the fin, and selectively removing the dummy gate to thereby expose the first portion of the first semiconductor layer portion that was enwrapped by the dummy gate. The method further includes introducing, into the exposed portion of the first semiconductor layer portion, one or more dopants including a conductivity type reversing dopant, so as to form a channel region having a first conductivity type and at least two opposed channel control regions having a second conductivity type, wherein the channel control regions further comprise a portion formed above and adjoining a top of the channel region.Type: GrantFiled: October 2, 2014Date of Patent: November 17, 2015Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventor: Mieno Fumitake
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Publication number: 20150311311Abstract: The present disclosure provides a static memory cell and fabrication method. A first fin part is formed on a semiconductor substrate. An isolation layer is formed to cover a lower portion of sidewalls of the first fin part. A first dummy gate structure is formed across the first fin part. A dielectric layer is formed on the isolation layer. A mask layer is formed on the dielectric layer with a first opening to expose the top surface of the first dummy gate structure. The first dummy gate structure is removed through the first opening to form a first trench exposing the first fin part. A portion of the isolation layer is removed through the first opening to form a second trench exposing a portion of sidewalls of the first fin part below the top surface of the isolation layer. A first gate structure is formed by filling up the first and the second trenches.Type: ApplicationFiled: April 15, 2015Publication date: October 29, 2015Inventor: MIENO FUMITAKE
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Publication number: 20150249148Abstract: A transistor includes a semiconductor substrate comprising a first region and a second region. The transistor further includes an emitter and a base disposed on the first region, and a collector disposed on the second region.Type: ApplicationFiled: October 14, 2014Publication date: September 3, 2015Inventor: Mieno FUMITAKE
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Patent number: 9117906Abstract: A method is provided for fabricating a fin field-effect transistor. The method includes providing a semiconductor substrate, and forming a plurality of fins with hard mask layers and an isolation structure. The process also includes forming a first dummy gate layer on the fins and the isolation structure, and polishing the first dummy gate layer until the hard mask layer is exposed. Further, the method includes removing the hard mask layer to expose a top surface of the fins, and forming a second dummy gate material layer on the first dummy gate material layer. Further, the method also includes etching the second dummy gate layer and the first dummy gate layer to form a dummy gate on each of the fins.Type: GrantFiled: April 12, 2013Date of Patent: August 25, 2015Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORPInventors: Mieno Fumitake, Huaxiang Yin
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Patent number: 9112020Abstract: Various embodiments provide transistor devices and fabrication methods. An exemplary transistor device with improved carrier mobility can be formed by first forming a confining layer on a semiconductor substrate to confine impurity ions diffused from the semiconductor substrate to the confining layer. An epitaxial silicon layer can be formed on the confining layer, followed by forming a gate structure on the epitaxial silicon layer. A portion of the epitaxial silicon layer can be used as an intrinsic channel region. A source region and a drain region can be formed in portions of each of the epitaxial silicon layer, the confining layer, and the semiconductor substrate.Type: GrantFiled: January 28, 2015Date of Patent: August 18, 2015Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORPInventors: Neil Zhao, Mieno Fumitake
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Patent number: 9064804Abstract: A method for manufacturing a twin bit cell structure with a silicon nitride material includes forming a gate dielectric layer overlying a semiconductor substrate and a polysilicon gate structure overlying the gate dielectric layer. An undercut region is formed in each side of the gate dielectric layer underneath the polysilicon gate structure. Thereafter, an oxidation process is performed to form a first silicon oxide layer on a peripheral surface of the polysilicon gate structure and a second silicon oxide layer on an exposed surface of the semiconductor substrate. Then, a silicon nitride material is deposited over the first and second silicon oxide layers including the undercut region and the gate dielectric layer. The silicon nitride material is selectively etched to form an insert region in a portion of the undercut region. A sidewall spacer is formed to isolate and protect the exposed silicon nitride material and the polysilicon gate structure.Type: GrantFiled: December 14, 2010Date of Patent: June 23, 2015Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventor: Mieno Fumitake
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Publication number: 20150171085Abstract: Various embodiments provide semiconductor devices and methods for forming the same. A first fin and a second fin are formed on a semiconductor substrate. A first dielectric layer is formed on the semiconductor substrate and has a top surface lower than a top surface of both of the first fin and the second fin. A gate structure is formed on the first dielectric layer and covering across a first portion of each of the first fin and the second fin. A second portion of the first fin on both sides of the gate structure is removed, forming a first recess. A first semiconductor layer is formed in the first recess. A second dielectric layer is formed on the first dielectric layer and the first semiconductor layer, and exposes a top surface of the second fin. A second semiconductor layer is formed on the exposed top surface of the second fin.Type: ApplicationFiled: December 18, 2014Publication date: June 18, 2015Inventors: MIENO FUMITAKE, JIANHUA JU
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Patent number: 9054193Abstract: A method is provided for fabricating a fin field-effect transistor. The method includes providing a semiconductor substrate; and forming a plurality of fins on top of the semiconductor substrate. The method also includes forming isolation structures between adjacent fins; and forming doping sidewall spacers in top portions of the isolation structures near the fins. Further, the method includes forming a punch-through stop layer at the bottom of each of the fins by thermal annealing the doping sidewall spacers; and forming a high-K metal gate on each of the fins.Type: GrantFiled: July 9, 2014Date of Patent: June 9, 2015Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventors: Huaxiang Yin, Mieno Fumitake
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Publication number: 20150137146Abstract: Various embodiments provide transistor devices and fabrication methods. An exemplary transistor device with improved carrier mobility can be formed by first forming a confining layer on a semiconductor substrate to confine impurity ions diffused from the semiconductor substrate to the confining layer. An epitaxial silicon layer can be formed on the confining layer, followed by forming a gate structure on the epitaxial silicon layer. A portion of the epitaxial silicon layer can be used as an intrinsic channel region. A source region and a drain region can be formed in portions of each of the epitaxial silicon layer, the confining layer, and the semiconductor substrate.Type: ApplicationFiled: January 28, 2015Publication date: May 21, 2015Inventors: NEIL ZHAO, MIENO FUMITAKE
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Patent number: 8975642Abstract: Various embodiments provide transistor devices and fabrication methods. An exemplary transistor device with improved carrier mobility can be formed by first forming a confining layer on a semiconductor substrate to confine impurity ions diffused from the semiconductor substrate to the confining layer. An epitaxial silicon layer can be formed on the confining layer, followed by forming a gate structure on the epitaxial silicon layer. A portion of the epitaxial silicon layer can be used as an intrinsic channel region. A source region and a drain region can be formed in portions of each of the epitaxial silicon layer, the confining layer, and the semiconductor substrate.Type: GrantFiled: November 27, 2012Date of Patent: March 10, 2015Assignee: Semiconductor Manufacturing International CorpInventors: Neil Zhao, Mieno Fumitake