Abstract: A method for fabricating semiconductor devices, e.g., SONOS cell. The method includes providing a semiconductor substrate (e.g., silicon wafer, silicon on insulator) having a surface region, which has a native oxide layer. The method includes treating the surface region to a wet cleaning process to remove a native oxide layer from the surface region. In a specific embodiment, the method includes subjecting the surface region to an oxygen bearing environment and subjecting the surface region to a high energy electromagnetic radiation having wavelengths ranging from about 300 to about 800 nanometers for a time period of less than 10 milli-seconds to increase a temperature of the surface region to greater than 1000 Degrees Celsius. In a specific embodiment, the method causes formation of an oxide layer having a thickness of less than 10 Angstroms. In a preferred embodiment, the oxide layer is substantially free from pinholes and other imperfections.

Abstract: A method and system for forming a non-volatile memory structure. The method provides a semiconductor substrate and forms a gate dielectric layer overlying a surface region of the semiconductor substrate. A polysilicon gate structure is formed overlying the gate dielectric layer. The method subjects the polysilicon gate structure to an oxidizing environment to cause formation of a first silicon oxide layer overlying the polysilicon gate structure and formation of a second silicon oxide layer overlying a surface region of the substrate. A hafnium oxide material is formed overlying the first and second silicon oxide layers and filling the undercut region. The hafnium oxide material has a nanocrystalline silicon material sandwiched between a first hafnium oxide layer and a second hafnium oxide layer. The hafnium oxide material is selectively etched while a portion of it is maintained in an insert region in a portion of the undercut region.

Abstract: A method for manufacturing a twin bit cell structure of with a hafnium oxide material includes providing a semiconductor substrate having a surface region and forming a gate dielectric layer overlying the surface region. The method forms a polysilicon gate structure overlying the gate dielectric layer and subjects the polysilicon gate structure to an oxidizing environment to cause formation of a first silicon oxide layer overlying the polysilicon gate structure. The method forms an undercut region underneath the polysilicon gate structure and subjects the polysilicon gate structure to an oxidization environment. Thereafter, the method forms a hafnium oxide material overlying the polysilicon gate structure including the undercut region and exposed portions of the gate dielectric layer. The hafnium oxide material is then selectively etched to form an insert region in a portion of the undercut region. A sidewall spacer is formed to isolate and protect the exposed hafnium oxide material.

Abstract: A method for forming a twin-bit cell structure is provided. The method includes providing a semiconductor substrate including a surface region. A gate dielectric layer is formed overlying the surface region. The method forms a polysilicon gate structure overlying the gate dielectric layer. In a specific embodiment, the method subjects the gate polysilicon structure to an oxidizing environment to cause formation of a first silicon oxide layer overlying the gate polysilicon structure. Preferably, an undercut region is allowed to be formed underneath the gate polysilicon structure. The method includes forming an undoped polysilicon material overlying the polysilicon gate structure including the undercut region and the gate dielectric layer. The undoped polysilicon material is subjected to a selective etching process to form an insert region in a portion of the undercut region while the insert region remains filled with the undoped polysilicon material.

Abstract: A method for manufacturing a twin bit cell structure with a silicon nitride material includes forming a gate dielectric layer overlying a semiconductor substrate and a polysilicon gate structure overlying the gate dielectric layer. An undercut region is formed in each side of the gate dielectric layer underneath the polysilicon gate structure. Thereafter, an oxidation process is performed to form a first silicon oxide layer on a peripheral surface of the polysilicon gate structure and a second silicon oxide layer on an exposed surface of the semiconductor substrate. Then, a silicon nitride material is deposited over the first and second silicon oxide layers including the undercut region and the gate dielectric layer. The silicon nitride material is selectively etched to form an insert region in a portion of the undercut region. A sidewall spacer is formed to isolate and protect the exposed silicon nitride material and the polysilicon gate structure.

Abstract: A method for manufacturing a twin bit cell structure with an aluminum oxide material includes forming a gate dielectric layer overlying a semiconductor substrate and a polysilicon gate structure overlying the gate dielectric layer. An undercut region is formed in each side of the gate dielectric layer underneath the polysilicon gate structure. Thereafter, an oxidation process is performed to form a first silicon oxide layer on a peripheral surface of the polysilicon gate structure and a second silicon oxide layer on an exposed surface of the semiconductor substrate. Then, an aluminum oxide material is deposited over the first and second silicon oxide layers including the undercut region and the gate dielectric layer. The aluminum oxide material is selectively etched to form an insert region in a portion of the undercut region. A sidewall spacer is formed to isolate and protect the exposed aluminum oxide material and the polysilicon gate structure.

Abstract: An improved semiconductor device, including a capacitor structure. The device has a first electrode member, which has a first length and a first width. The device also has a second electrode member, which has a second length and a second width. Additionally, the device includes a capacitor dielectric material provided between the first electrode member and the second electrode member according to a specific embodiment. Depending upon the embodiment, the capacitor dielectric material is made of a suitable material or materials such as Al2O3, HfO2, SiN, NO, Al2O3/HfO2, AlNyOx, ZrO2, any combinations of these, and the like. The device further includes a plurality of silicon nanocrystals spatially disposed in an area associated with the first width and the first length of the first electrode member. Each one of the nanocrystals has a size of about 20 nanometers and less according to a specific embodiment.

Abstract: A method for forming a nanocrystalline silicon structure for the manufacture of integrated circuit devices, e.g., memory, dynamic random access memory, flash memory, read only memory, microprocessors, digital signal processors, application specific integrated circuits. The method includes providing a semiconductor substrate including a surface region. The method forms an insulating layer (e.g., silicon dioxide, silicon nitride, silicon oxynitride) overlying the surface region. In a specific embodiment, the method includes forming an amorphous silicon material of a determined thickness of less than twenty nanometers overlying the insulating layer using a chloro-silane species. The method includes subjecting the amorphous silicon material to a thermal treatment process to cause formation of a plurality of nanocrsytalline silicon structures derived from the thickness of amorphous silicon material less than twenty nanometers.

Abstract: A method for forming a nanocrystalline silicon structure for the manufacture of integrated circuit devices, e.g., memory, dynamic random access memory, flash memory, read only memory, microprocessors, digital signal processors, application specific integrated circuits. In a specific embodiment, the present invention includes providing a semiconductor substrate including a surface region. The method includes forming an insulating layer (e.g., silicon dioxide, silicon nitride, silicon oxynitride) overlying the surface region according to a specific embodiment. The method includes forming an amorphous silicon material of a determined thickness of less than twenty nanometers overlying the insulating layer. The method includes subjecting the amorphous silicon material to a thermal treatment process to cause formation of a plurality of nanocrsytalline silicon structures derived from the thickness of amorphous silicon material less than twenty nanometers.

Abstract: A method and system for forming a non-volatile memory structure. The method includes providing a semiconductor substrate and forming a gate dielectric layer overlying a surface region of the semiconductor substrate. A polysilicon gate structure is formed overlying the gate dielectric layer. The method subjects the polysilicon gate structure to an oxidizing environment to cause formation of a first silicon oxide layer overlying the polysilicon gate structure and formation of an undercut region underneath the polysilicon gate structure. An aluminum oxide material is formed overlying the polysilicon gate structure filling the undercut region. In a specific embodiment, the aluminum oxide material has a nanocrystalline silicon material sandwiched between a first aluminum oxide layer and a second aluminum oxide layer. The aluminum oxide material is subjected to a selective etching process while maintaining the aluminum oxide material in an insert region in a portion of the undercut region.

Abstract: A semiconductor device with an amorphous silicon (a-Si) metal-oxide-nitride-oxide-silicon (MONOS) or metal-aluminum oxide-silicon (MAS) memory cell structure with one-time programmable (OTP) function. The device includes a substrate, a first dielectric layer overlying the substrate, and one or more source or drain regions embedded in the first dielectric layer with a co-planar surface of n-type a-Si and the first dielectric layer. Additionally, the device includes a p-i-n a-Si diode junction. The device further includes a second dielectric layer on the a-Si p-i-n diode junction and a metal control gate overlying the second dielectric layer. Optionally the device with OTP function includes a conductive path formed between n-type a-Si layer and the metal control gate. A method of making the same memory cell structure is provided and can be repeated to integrate the structure three-dimensionally.

Abstract: A semiconductor device with an amorphous silicon (a-Si) metal-oxide-nitride-oxide-semiconductor (MONOS) memory cell structure. The device includes a substrate, a dielectric layer overlying the substrate, and one or more source or drain regions embedded in the dielectric layer with a co-planar surface of n-type a-Si and the dielectric layer. Additionally, the device includes a p-i-n a-Si diode junction. The device further includes an oxide-nitride-oxide (ONO) charge trapping layer overlying the a-Si p-i-n diode junction and a metal control gate overlying the ONO layer. A method for making the a-Si MONOS memory cell structure is provided and can be repeated to expand the structure three-dimensionally.

Abstract: A semiconductor device with an amorphous silicon (a-Si) metal-oxide-nitride-oxide-semiconductor (MONOS) memory cell structure. The device includes a substrate, a dielectric layer overlying the substrate, and one or more source or drain regions embedded in the dielectric layer with a co-planar surface of n-type a-Si and the dielectric layer. Additionally, the device includes a p-i-n a-Si diode junction. The device further includes an oxide-nitride-oxide (ONO) charge trapping layer overlying the a-Si p-i-n diode junction and a metal control gate overlying the ONO layer. A method for making the a-Si MONOS memory cell structure is provided and can be repeated to expand the structure three-dimensionally.

Abstract: An improved image sensor, e.g., CCD, CID, CMOS. The image sensor includes a substrate, e.g., silicon wafer. The sensor also includes a plurality of photo diode regions, where each of the photo diode regions is spatially disposed on the substrate. The sensor has an interlayer dielectric layer overlying the plurality of photo diode regions and a shielding layer formed overlying the interlayer dielectric layer. A silicon dioxide bearing material is overlying the shielding layer. A plurality of lens structures are formed on the silicon dioxide bearing material. The sensor also has a color filter layer overlying the lens structures and a plurality of second lens structures overlying the color filter layer according to a preferred embodiment.

Abstract: A semiconductor device with an amorphous silicon (a-Si) metal-oxide-nitride-oxide-semiconductor (MONOS) memory cell structure. The device includes a substrate, a dielectric layer overlying the substrate, and one or more source or drain regions embedded in the dielectric layer with a co-planar surface of n-type a-Si and the dielectric layer. Additionally, the device includes a p-i-n a-Si diode junction. The device further includes an oxide-nitride-oxide (ONO) charge trapping layer overlying the a-Si p-i-n diode junction and a metal control gate overlying the ONO layer. A method for making the a-Si MONOS memory cell structure is provided and can be repeated to expand the structure three-dimensionally.

Abstract: A method for forming bit line and storage node contacts for a dynamic random access device, e.g., DRAM. Other devices (e.g., Flash, EEPROM) may also be included. The method includes providing a substrate, which has a bit line region and a capacitor contact region. The method also includes forming at least a first gate structure and a second gate structure overlying the substrate. The first gate structure and the second gate structure include an overlying cap. The method also includes forming a conformal dielectric layer overlying the first gate structure, the second gate structure, the bit line region, and the capacitor contact region. The method includes forming an interlayer dielectric material overlying the conformal dielectric layer and planarizing the interlayer dielectric material.

Abstract: A method for forming bit line and storage node contacts for a dynamic random access device, e.g., DRAM. Other devices (e.g., Flash, EEPROM) may also be included. The method includes providing a substrate, which has a bit line region and a capacitor contact region. The method also includes forming at least a first gate structure and a second gate structure overlying the substrate. The first gate structure and the second gate structure include an overlying cap. The method also includes forming a conformal dielectric layer overlying the first gate structure, the second gate structure, the bit line region, and the capacitor contact region. The method includes forming an interlayer dielectric material overlying the conformal dielectric layer and planarizing the interlayer dielectric material.