Abstract: The present disclosure relates to a magnetic tunnel junction (MTJ) device and its fabricating method. Through forming MTJ through a damascene process, device damage due to the etching process and may be avoided. In some embodiments, a spacer is formed between a first portion and a second portion of the MTJ to prevent the tunnel insulating layer of the MTJ from being damaged in subsequent processes, greatly increasing product yield thereby. In other embodiments, signal quality may be improved and magnetic flux leakage may be reduced through the improved cup-shaped MTJ structure of this invention.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes providing a fin protruding upwardly from or through a surface of a substrate, forming a to-be-sacrificed dummy gate enwrapping a first portion of the fin, forming a first insulating material layer so as to at least cover an exposed second portion of the fin, and selectively removing the dummy gate to thereby expose the first portion of the first semiconductor layer portion that was enwrapped by the dummy gate. The method further includes introducing, into the exposed portion of the first semiconductor layer portion, one or more dopants including a conductivity type reversing dopant, so as to form a channel region having a first conductivity type and at least two opposed channel control regions having a second conductivity type, wherein the channel control regions further comprise a portion formed above and adjoining a top of the channel region.

Abstract: A non-planar JFET device having a thin fin structure is provided. A fin is formed projecting upwardly from or through a top surface of a substrate, where the fin has a first semiconductor layer portion formed from a first semiconductor material of a first conductivity type. The first semiconductor layer portion has a source region and a drain region, a channel region extending between the source region and the drain region. Two or more channel control regions are formed adjoining the channel region for generating charge depletion zones at and extending into the channel region for thereby controlling current conduction through the channel region. A gate is provided so as to adjoin and short together the at least two channel control regions from the outer sides of the channel control regions.

Abstract: The present disclosure relates to a magnetic tunnel junction (MTJ) device and its fabricating method. Through forming MTJ through a damascene process, device damage due to the etching process and may be avoided. In some embodiments, a spacer is formed between a first portion and a second portion of the MTJ to prevent the tunnel insulating layer of the MTJ from being damaged in subsequent processes, greatly increasing product yield thereby. In other embodiments, signal quality may be improved and magnetic flux leakage may be reduced through the improved cup-shaped MTJ structure of this invention.

Abstract: A method is provided for fabricating a fin field-effect transistor. The method includes providing a semiconductor substrate having one or more first fins and second fins; and forming a first doping layer covering the first fins and the second fins. The method also includes forming an isolation layer to isolate adjacent fins; and forming a gate structure stretching across top and sidewalls of the first fins. Further, the method includes forming a source region and a drain region in the fins at both sides of the gate structure; and forming a dielectric layer on the isolation layer. Further, the method also includes forming a first through hole in the dielectric layer to expose a portion of the first doping layer on a top of the second fins; and forming a first conductive via in the first through hole to connect with a bias control voltage.

Abstract: The disclosure relates to a complementary junction field effect transistor (c-JFET) and its gate-last fabrication method. The method of fabricating a semiconductor device includes: forming a dummy gate on a first conductivity type wafer, forming sidewall spacers on opposite sides of the dummy gate, forming a source and a drain regions on the opposite sides of the dummy gate, removing the dummy gate, forming a first semiconductor region of a second conductivity type in an opening exposed through the removing the dummy gate, and forming a gate electrode in the opening.

Abstract: A method is provided for fabricating a fin field-effect transistor. The method includes providing a semiconductor substrate; and forming a plurality of fins on top of the semiconductor substrate. The method also includes forming isolation structures between adjacent fins; and forming doping sidewall spacers in top portions of the isolation structures near the fins. Further, the method includes forming a punch-through stop layer at the bottom of each of the fins by thermal annealing the doping sidewall spacers; and forming a high-K metal gate on each of the fins.

Abstract: A non-planar JFET device having a thin fin structure is provided. A fin is formed projecting upwardly from or through a top surface of a substrate, where the fin has a first semiconductor layer portion formed from a first semiconductor material of a first conductivity type. The first semiconductor layer portion has a source region and a drain region, a channel region extending between the source region and the drain region. Two or more channel control regions are formed adjoining the channel region for generating charge depletion zones at and extending into the channel region for thereby controlling current conduction through the channel region. A gate is provided so as to adjoin and short together the at least two channel control regions from the outer sides of the channel control regions.

Abstract: The present disclosure relates to a magnetic tunnel junction (MTJ) device and its fabricating method. Through forming MTJ through a damascene process, device damage due to the etching process and may be avoided. In some embodiments, a spacer is formed between a first portion and a second portion of the MTJ to prevent the tunnel insulating layer of the MTJ from being damaged in subsequent processes, greatly increasing product yield thereby. In other embodiments, signal quality may be improved and magnetic flux leakage may be reduced through the improved cup-shaped MTJ structure of this invention.

Abstract: A method is provided for fabricating a fin field-effect transistor. The method includes providing a semiconductor substrate; and forming a plurality of fins on top of the semiconductor substrate. The method also includes forming isolation structures between adjacent fins; and forming doping sidewall spacers in top portions of the isolation structures near the fins. Further, the method includes forming a punch-through stop layer at the bottom of each of the fins by thermal annealing the doping sidewall spacers; and forming a high-K metal gate on each of the fins.

Abstract: A method is provided for fabricating a fin field-effect transistor. The method includes providing a semiconductor substrate; and forming a plurality of fins on top of the semiconductor substrate. The method also includes forming isolation structures between adjacent fins; and forming doping sidewall spacers in top portions of the isolation structures near the fins. Further, the method includes forming a punch-through stop layer at the bottom of each of the fins by thermal annealing the doping sidewall spacers; and forming a high-K metal gate on each of the fins.

Abstract: A method for forming image sensors includes providing a substrate and forming a plurality of photo diode regions, each of the photo diode regions being spatially disposed on the substrate. The method also includes forming an interlayer dielectric layer overlying the plurality of photo diode regions, forming a shielding layer formed overlying the interlayer dielectric layer, and applying a silicon dioxide bearing material overlying the shielding layer. The method further includes etching portions of the silicon dioxide bearing material to form a plurality of first lens structures, and continuing to form each of the plurality of first lens structures to provide a plurality of finished lens structures.

Abstract: A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate having a first region and an adjacent second region, and etching the semiconductor substrate to form a plurality of first trenches in the first region and a second trench in the second region. Fins are formed in between the adjacent first trenches. The width of the second trench is greater than the width of the first trench. The method also includes filling the first trenches with a first isolation material to form first insolation structures, and form sidewall spacers inside the second trench. Further, the method includes forming a third trench in the second trench by etching the exposed semiconductor substrate on the bottom of the second trench using the sidewall spacers as an etching mask, and filling the second trench and the third trench using a second isolation material to form a second isolation structure.

Abstract: A method for fabricating a semiconductor structure includes providing a semiconductor substrate having a first region and a second region, and doping top of the semiconductor substrate to form a doped layer at top surface of the semiconductor substrate over the first region and the second region. The method also includes etching the doped layer to form a first sub-fin in the first region and a first sub-fin in the second region, and forming an insulating layer over the semiconductor substrate including the first sub-fin in the first region and the first sub-fin in the second region. Further, the method includes removing top portions of the first sub-fin in the first region and the first sub-fin in the second region and forming corresponding second sub-fins.

Abstract: An improved image sensor, e.g., CCD, CID, CMOS. The image sensor includes a substrate, e.g., silicon wafer. The sensor also includes a plurality of photo diode regions, where each of the photo diode regions is spatially disposed on the substrate. The sensor has an interlayer dielectric layer overlying the plurality of photo diode regions and a shielding layer formed overlying the interlayer dielectric layer. A silicon dioxide bearing material is overlying the shielding layer. A plurality of lens structures are formed on the silicon dioxide bearing material. The sensor also has a color filter layer overlying the lens structures and a plurality of second lens structures overlying the color filter layer according to a preferred embodiment.

Abstract: A method for forming a nanocrystalline silicon structure for the manufacture of integrated circuit devices, e.g., memory, dynamic random access memory, flash memory, read only memory, microprocessors, digital signal processors, application specific integrated circuits. In a specific embodiment, the present invention includes providing a semiconductor substrate including a surface region. The method includes forming an insulating layer (e.g., silicon dioxide, silicon nitride, silicon oxynitride) overlying the surface region according to a specific embodiment. The method includes forming an amorphous silicon material of a determined thickness of less than twenty nanometers overlying the insulating layer. The method includes subjecting the amorphous silicon material to a thermal treatment process to cause formation of a plurality of nanocrystalline silicon structures derived from the thickness of amorphous silicon material less than twenty nanometers.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The fin semiconductor device includes a fin formed on a substrate and an insulating material layer formed on the substrate and surrounding the fin. The fin has a semiconductor layer that has a source region portion and a drain region portion. The fin includes a first channel control region, a second channel control region, and a channel region between the two channel control regions, all of which are positioned between the source region portion and the drain region portion. The two channel control regions may have the same conductivity type, different from the channel region.

Abstract: A semiconductor device is described as including a first fin having a layer formed of a first semiconductor material and a second fin that is formed of a second semiconductor material. The first and second semiconductor materials are different. The second semiconductor material may have a mobility of P-type carriers that is greater than a mobility of P-type carriers of the first semiconductor material. The second fin includes a layer formed of the first semiconductor material below the layer formed of the second semiconductor material. The semiconductor device further includes a hard mask layer disposed on the first and second fins and an insulator layer disposed below the first and second fins. The first and second semiconductor materials include silicon and germanium, respectively. The first and second fins are used to form respective N-channel and a P-channel semiconductor devices.

Abstract: The present invention discloses a semiconductor device and a method for manufacturing the semiconductor device. The semiconductor device includes a gate insulating layer formed on an inner wall of a substrate recess, a work function material layer formed on the gate insulating layer so as to apply a tensile stress or a compressive stress to a channel of a MOS field-effect transistor, and a gate metal formed on the work function material layer. The method for manufacturing the semiconductor device includes forming a work function material layer on a gate insulating layer so as to apply a tensile stress or a compressive stress to a channel of a MOS field-effect transistor, wherein the gate insulating layer is formed on an inner wall of a substrate recess, and depositing a gate metal on the work function material layer.

Abstract: A method for forming a nanocrystalline silicon structure for the manufacture of integrated circuit devices, e.g., memory, dynamic random access memory, flash memory, read only memory, microprocessors, digital signal processors, application specific integrated circuits. The method includes providing a semiconductor substrate including a surface region. The method forms an insulating layer (e.g., silicon dioxide, silicon nitride, silicon oxynitride) overlying the surface region. In a specific embodiment, the method includes forming an amorphous silicon material of a determined thickness of less than twenty nanometers overlying the insulating layer using a chloro-silane species. The method includes subjecting the amorphous silicon material to a thermal treatment process to cause formation of a plurality of nanocrystalline silicon structures derived from the thickness of amorphous silicon material less than twenty nanometers.