Patents by Inventor Mihaela A. Balseanu

Mihaela A. Balseanu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8084105
    Abstract: Methods for forming boron-containing films are provided. The methods include introducing a boron-containing precursor and a nitrogen or oxygen-containing precursor into a chamber and forming a boron nitride or boron oxide film on a substrate in the chamber. In one aspect, the method includes depositing a boron-containing film and then exposing the boron-containing film to the nitrogen-containing or oxygen-containing precursor to incorporate nitrogen or oxygen into the film. The deposition of the boron-containing film and exposure of the film to the precursor may be performed for multiple cycles to obtain a desired thickness of the film. In another aspect, the method includes reacting the boron-containing precursor and the nitrogen-containing or oxygen-containing precursor to chemically vapor deposit the boron nitride or boron oxide film.
    Type: Grant
    Filed: June 19, 2007
    Date of Patent: December 27, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Jeong-Uk Huh, Mihaela Balseanu, Li-Qun Xia, Victor T. Nguyen, Derek R. Witty, Hichem M'Saad
  • Publication number: 20110104891
    Abstract: A method and apparatus for generating air gaps in a dielectric material of an interconnect structure. One embodiment provides a method for forming a semiconductor structure comprising depositing a first dielectric layer on a substrate, forming trenches in the first dielectric layer, filling the trenches with a conductive material, planarizing the conductive material to expose the first dielectric layer, depositing a dielectric barrier film on the conductive material and exposed first dielectric layer, depositing a hard mask layer over the dielectric barrier film, forming a pattern in the dielectric barrier film and the hard mask layer to expose selected regions of the substrate, oxidizing at least a portion of the first dielectric layer in the selected region of the substrate, removing oxidized portion of the first dielectric layer to form reversed trenches around the conductive material, and forming air gaps in the reversed trenches while depositing a second dielectric material in the reversed trenches.
    Type: Application
    Filed: January 7, 2011
    Publication date: May 5, 2011
    Inventors: AMIR AL-BAYATI, Alexandros T. Demos, Kang Sub Yim, Mehul Naik, Zhenjiang David Cui, Mihaela Balseanu, Meiyee Maggie Le Shek, Li-Qun Xia
  • Patent number: 7923386
    Abstract: A method of forming a layer on a substrate in a chamber, wherein the substrate has at least one formed feature across its surface, is provided. The method includes exposing the substrate to a silicon-containing precursor in the presence of a plasma to deposit a layer, treating the deposited layer with a plasma, and repeating the exposing and treating until a desired thickness of the layer is obtained. The plasma may be generated from an oxygen-containing gas.
    Type: Grant
    Filed: September 16, 2009
    Date of Patent: April 12, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Mihaela Balseanu, Mei-yee Shek, Li-Qun Xia, Hichem M'Saad
  • Patent number: 7910491
    Abstract: A method of filling a trench is described and includes depositing a dielectric liner with a high ratio of silicon oxide to dielectric liner etch rate in fluorine-containing etch chemistries. Silicon oxide is deposited within the trench and etched to reopen or widen a gap near the top of the trench. The dielectric liner protects the underlying substrate during the etch process so the gap can be made wider. Silicon oxide is deposited within the trench again to substantially fill the trench.
    Type: Grant
    Filed: May 7, 2009
    Date of Patent: March 22, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Young Soo Kwon, Bi Jang, Anchuan Wang, Young S. Lee, Mihaela Balseanu, Li-Qun Xia, Jin Ho Jeon
  • Patent number: 7879683
    Abstract: A method and apparatus for generating air gaps in a dielectric material of an interconnect structure. One embodiment provides a method for forming a semiconductor structure comprising depositing a first dielectric layer on a substrate, forming trenches in the first dielectric layer, filling the trenches with a conductive material, planarizing the conductive material to expose the first dielectric layer, depositing a dielectric barrier film on the conductive material and exposed first dielectric layer, depositing a hard mask layer over the dielectric barrier film, forming a pattern in the dielectric barrier film and the hard mask layer to expose selected regions of the substrate, oxidizing at least a portion of the first dielectric layer in the selected region of the substrate, removing oxidized portion of the first dielectric layer to form reversed trenches around the conductive material, and forming air gaps in the reversed trenches while depositing a second dielectric material in the reversed trenches.
    Type: Grant
    Filed: October 9, 2007
    Date of Patent: February 1, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Amir Al-Bayati, Alexandros T. Demos, Kang Sub Yim, Mehul Naik, Zhenjiang “David” Cui, Mihaela Balseanu, Meiyee (Maggie Le) Shek, Li-Qun Xia
  • Patent number: 7871926
    Abstract: A method for forming a structure includes forming at least one feature across a surface of a substrate. A nitrogen-containing dielectric layer is formed over the at least one feature. A first portion of the nitrogen-containing layer on at least one sidewall of the at least one feature is removed at a first rate and a second portion of the nitrogen-containing layer over the substrate adjacent to a bottom region of the at least one feature is removed at a second rate. The first rate is greater than the second rate. A dielectric layer is formed over the nitrogen-containing dielectric layer.
    Type: Grant
    Filed: October 22, 2007
    Date of Patent: January 18, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Li-Qun Xia, Mihaela Balseanu, Victor Nguyen, Derek R. Witty, Hichem M'Saad, Haichun Yang, Xinliang Lu, Chien-Teh Kao, Mei Chang
  • Patent number: 7816205
    Abstract: A flash memory device and method of forming a flash memory device are provided. The flash memory device includes a silicon nitride layer having a compositional gradient in which the ratio of silicon to nitrogen varies through the thickness of the layer. The silicon nitride layer having a compositional gradient of silicon and nitrogen provides an increase in charge holding capacity and charge retention time of the unit cell of a non-volatile memory device.
    Type: Grant
    Filed: October 22, 2008
    Date of Patent: October 19, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Mihaela Balseanu, Vladimir Zubkov, Li-Qun Xia, Atif Noori, Reza Arghavani, Derek R. Witty, Amir Al-Bayati
  • Publication number: 20100233633
    Abstract: Methods for processing a substrate with a boron rich film are provided. A patterned layer of boron rich material is deposited on a substrate and can be used as an etch stop. By varying the chemical composition, the selectivity and etch rate of the boron rich material can be optimized for different etch chemistries. The boron rich materials can be deposited over a layer stack substrate in multiple layers and etched in a pattern. The exposed layer stack can then be etched with multiple etch chemistries. Each of the boron rich layers can have a different chemical composition that is optimized for the multiple etch chemistries.
    Type: Application
    Filed: May 24, 2010
    Publication date: September 16, 2010
    Applicant: Applied Materials, Inc.
    Inventors: Victor Nguyen, Yi Chen, Mihaela Balseanu, Isabelita Roflox, Li-Qun Xia, Derek R. Witty
  • Patent number: 7790635
    Abstract: A method for forming a compressive stress carbon-doped silicon nitride layer is provided. The method includes forming an initiation layer and a bulk layer thereon, wherein the bulk layer has a compressive stress of between about ?0.1 GPa and about ?10 GPa. The initiation layer is deposited from a gas mixture that includes a silicon and carbon-containing precursor and optionally a nitrogen and/or source but does not include hydrogen gas. The bulk layer is deposited from a gas mixture that includes a silicon and carbon-containing precursor, a nitrogen source, and hydrogen gas. The initiation layer is a thin layer that allows good transfer of the compressive stress of the bulk layer therethrough to an underlying layer, such as a channel of a transistor.
    Type: Grant
    Filed: December 14, 2006
    Date of Patent: September 7, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Mihaela Balseanu, Victor T. Nguyen, Li-Qun Xia, Vladimir Zubkov, Derek R. Witty, Hichem M'Saad
  • Patent number: 7780865
    Abstract: Methods of controlling the step coverage and pattern loading of a layer on a substrate are provided. The dielectric layer may be a silicon nitride, silicon oxide, or silicon oxynitride layer. The method comprises depositing a dielectric layer on a substrate having at least one formed feature across a surface of the substrate and etching the dielectric layer with a plasma from oxygen or a halogen-containing gas to provide a desired profile of the dielectric layer on the at least one formed feature. The deposition of the dielectric layer and the etching of the dielectric layer may be repeated for multiple cycles to provide the desired profile of the dielectric layer.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: August 24, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Mihaela Balseanu, Li-Qun Xia, Mei-Yee Shek, Hichem M'Saad
  • Patent number: 7732342
    Abstract: Compressive stress in a film of a semiconductor device may be controlled utilizing one or more techniques, employed alone or in combination. A first set of embodiments increase silicon nitride compressive stress by adding hydrogen to the deposition chemistry, and reduce defects in a device fabricated with a high compressive stress silicon nitride film formed in the presence of hydrogen gas. A silicon nitride film may comprise an initiation layer formed in the absence of a hydrogen gas flow, underlying a high stress nitride layer formed in the presence of a hydrogen gas flow. A silicon nitride film formed in accordance with an embodiment of the present invention may exhibit a compressive stress of 2.8 GPa or higher.
    Type: Grant
    Filed: April 5, 2006
    Date of Patent: June 8, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Mihaela Balseanu, Li-Qun Xia, Vladimir Zubkov, Mei-Yee Shek, Isabelita Rolfox, Hichem M'Saad
  • Patent number: 7704816
    Abstract: Methods of forming boron-containing films are provided. The methods include introducing a boron-containing precursor into a chamber and depositing a network comprising boron-boron bonds on a substrate by thermal decomposition or a plasma process. The network may be post-treated to remove hydrogen from the network and increase the stress of the resulting boron-containing film. The boron-containing films have a stress between about ?10 GPa and 10 GPa and may be used as boron source layers or as strain-inducing layers.
    Type: Grant
    Filed: July 11, 2008
    Date of Patent: April 27, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Jeong-Uk Huh, Mihaela Balseanu, Li-Qun Xia, Derek R. Witty, Hichem M'Saad
  • Publication number: 20100099247
    Abstract: A methods of forming a flash memory device are provided. The flash memory device comprises a silicon dioxide layer on a substrate and a silicon nitride layer that is formed on the silicon dioxide layer. The properties of the silicon nitride layer can be modified by any of: exposing the silicon nitride layer to ultraviolet radiation, exposing the silicon nitride layer to an electron beam, and by plasma treating the silicon nitride layer. A dielectric material is deposited on the silicon nitride layer and a conductive date is formed over the dielectric material. The flash memory device with modified silicon nitride layer provides an increase in charge holding capacity and charge retention time of the unit cell of a non-volatile memory device.
    Type: Application
    Filed: October 22, 2008
    Publication date: April 22, 2010
    Inventors: Mihaela Balseanu, Vladimir Zubkov, Li-Qun Xia, Atif Noori, Reza Arghavani, Derek R. Witty, Amir Al-Bayati
  • Publication number: 20100096687
    Abstract: A flash memory device and methods of forming a flash memory device are provided. The flash memory device includes a doped silicon nitride layer having a dopant comprising carbon, boron or oxygen. The doped silicon nitride layer generates a higher number and higher concentration of nitrogen and silicon dangling bonds in the layer and provides an increase in charge holding capacity and charge retention time of the unit cell of a non-volatile memory device.
    Type: Application
    Filed: October 21, 2008
    Publication date: April 22, 2010
    Inventors: Mihaela BALSEANU, Vladimir Zubkov, Li-Qun Xia, Atif Noori, Reza Arghavani, Derek R. Witty, Amir Al-Bayati
  • Publication number: 20100099236
    Abstract: A method of filling a trench is described and includes depositing a dielectric liner with a high ratio of silicon oxide to dielectric liner etch rate in fluorine-containing etch chemistries. Silicon oxide is deposited within the trench and etched to reopen or widen a gap near the top of the trench. The dielectric liner protects the underlying substrate during the etch process so the gap can be made wider. Silicon oxide is deposited within the trench again to substantially fill the trench.
    Type: Application
    Filed: May 7, 2009
    Publication date: April 22, 2010
    Applicant: Applied Materials, Inc.
    Inventors: Young Soo Kwon, Bi Jang, Anchuan Wang, Young S. Lee, Mihaela Balseanu, Li-Qun Xia, Jin Ho Jeon
  • Publication number: 20100096688
    Abstract: A flash memory device and method of forming a flash memory device are provided. The flash memory device includes a silicon nitride layer having a compositional gradient in which the ratio of silicon to nitrogen varies through the thickness of the layer. The silicon nitride layer having a compositional gradient of silicon and nitrogen provides an increase in charge holding capacity and charge retention time of the unit cell of a non-volatile memory device.
    Type: Application
    Filed: October 22, 2008
    Publication date: April 22, 2010
    Inventors: Mihaela Balseanu, Vladimir Zubkov, Li-Qun Xia, Atif Noori, Reza Arghavani, Derek R. Witty, Amir Al-Bayati
  • Publication number: 20100098884
    Abstract: Methods of depositing boron-containing liner layers on substrates involve the formation of a bilayer including an initiation layer which includes barrier material to inhibit the diffusion of boron from the bilayer into the underlying substrate.
    Type: Application
    Filed: June 22, 2009
    Publication date: April 22, 2010
    Applicant: Applied Materials, Inc.
    Inventors: MIHAELA BALSEANU, Li-Qun Xia, Derek R. Witty, Yi Chen
  • Publication number: 20100048030
    Abstract: A method of forming a layer on a substrate in a chamber, wherein the substrate has at least one formed feature across its surface, is provided. The method includes exposing the substrate to a silicon-containing precursor in the presence of a plasma to deposit a layer, treating the deposited layer with a plasma, and repeating the exposing and treating until a desired thickness of the layer is obtained. The plasma may be generated from an oxygen-containing gas.
    Type: Application
    Filed: September 16, 2009
    Publication date: February 25, 2010
    Applicant: APPLIED MATERIALS, INC.
    Inventors: MIHAELA BALSEANU, Meiyee Shek, Li-Qun Xia, Hichem M'Saad
  • Publication number: 20090286402
    Abstract: A method and apparatus for forming narrow vias in a substrate is provided. A pattern recess is etched into a substrate by conventional lithography. A thin conformal layer is formed over the surface of the substrate, including the sidewalls and bottom of the pattern recess. The thickness of the conformal layer reduces the effective width of the pattern recess. The conformal layer is removed from the bottom of the pattern recess by anisotropic etching to expose the substrate beneath. The substrate is then etched using the conformal layer covering the sidewalls of the pattern recess as a mask. The conformal layer is then removed using a wet etchant.
    Type: Application
    Filed: October 23, 2008
    Publication date: November 19, 2009
    Applicant: APPLIED MATERIALS, INC
    Inventors: Li-Qun Xia, Mihaela Balseanu, Meiyee Shek, Siyi Li, Zhenjiang Cui, Mehul B. Naik, Michael D. Armacost, William H. McClintock
  • Patent number: 7615788
    Abstract: A device and method of forming electronics and microelectromechanical on a silicon carbide substrate having a slow etch rate is performed by forming circuitry on the substrate. A protective layer is formed over the circuitry having a slower etch rate than the etch rate of the silicon carbide substrate. Microelectromechanical structures supported by the substrate are then formed. The circuitry comprises a field effect transistor in one embodiment, and the protective layer comprises a heavy metal layer.
    Type: Grant
    Filed: January 29, 2007
    Date of Patent: November 10, 2009
    Assignee: Cornell Research Foundation, Inc.
    Inventors: Kevin Kornegay, Andrew R. Atwell, Mihaela Balseanu, Jon Duster, Eskinder Hailu, Ce Li