Abstract: A trench DMOS transistor includes a buried layer region formed between the drain region and overlying drift region and having a doping type the same as that of the drift region and drain region. The buried layer region is more highly doped than the drain region or drift regions and is formed by e.g. implantation prior to epitaxial growth of the overlying drift region. By providing an optimized doping profile for the buried layer region, it is ensured that avalanche breakdown occurs at the buried layer region/body region. Thus drain-source on resistance is reduced because the JFET region present in prior art devices is eliminated, while device ruggedness and reliability are enhanced.

Abstract: A trenched field effect transistor suitable especially for low voltage power applications provides low leakage blocking capability due to a gate controlled barrier region between the source region and drain region. Forward conduction occurs through an inversion region between the source region and drain region. Blocking is achieved by a gate controlled depletion barrier. Located between the source and drain regions is a fairly lightly doped body region. The gate electrode, located in a trench, extends through the source and body regions and in some cases into the upper portion of the drain region. The dopant type of the polysilicon gate electrode is the same type as that of the body region. The body region is a relatively thin and lightly doped epitaxial layer grown upon a highly doped low resistivity substrate of opposite conductivity type. In the blocking state the epitaxial body region is depleted due to applied drain-source voltage, hence a punch-through type condition occurs vertically.

Abstract: A trenched DMOS transistor is fabricated using seven masking steps. One masking step defines both the P+ deep body regions and the active portions of the transistor which are masked using a LOCOS process. A second masking step defines the insulating oxide in the termination region. The insulating (oxide) layer in the termination region is thus thicker than in the active region of the transistor, thereby improving process control and reducing substrate contamination during processing. Additionally, the thicker field oxide in the termination region improves electric field distribution so that avalanche breakdown occurs in the cell (active) region rather than in the termination region, and thus breakdown voltage behavior is more stable and predictable.

Abstract: To reduce susceptibility to punchthrough, the channel region of the P body region of a trench field effect transistor is formed in a layer of lightly doped epitaxial silicon. As a result, the channel region has less counterdoping from the background epitaxial silicon and has a greater net P type dopant concentration. Due to the higher net dopant concentration of the P body region, the depletion regions on either side of the P body region expand less far inward through the P body region at a given voltage, thereby rendering the transistor less susceptible to source-to-drain punchthrough. To maintain a low R.sub.DSon, the relatively high conductivity of an accumulation region formed along a sidewall of the trench of the transistor when the transistor is on is used to form a conductive path from the channel region to an underlying relatively highly conductive layer upon which the lightly doped epitaxial layer is formed.

Abstract: A DMOS field effect transistor having its gate electrode located in a trench includes a lightly doped epitaxial layer overlying the usual epitaxial layer. The trench penetrates only part way through the upper epitaxial layer which is more lightly doped than is the underlying lower epitaxial layer. The lightly doped upper epitaxial layer reduces the electric field at the bottom of the trench, thus protecting the gate oxide from breakdown during high voltage operation. Advantageously the upper portion of the lightly doped upper epitaxial layer has little adverse effect on the transistor's on resistance.

Abstract: The present invention detects defects near the gate/trench-surface interface of trench transistors. Defects near this interface which cause long term reliability problems generally also result in charges being trapped near the interface. In accordance with one embodiment of the present invention, a negative voltage is applied to the gate of the trench transistor with its drain grounded and its source floating. A leakage current flowing between the gate and drain is measured as a function of the voltage applied to the gate. A transistor whose gate-drain leakage current exceeds a predetermined value at a specified gate voltage is deemed to be defective. In another embodiment of the present invention, the gate-drain leakage current is measured as described above and monitored over time. Charge accumulated near the gate-drain interface due to defects in the interface results in the gate-drain leakage current taking a longer period of time to fall off to its steady state value.

Abstract: A DMOS transistor having a trenched gate is formed in a substrate such that the P body region of the transistor may be formed heavier or deeper while still maintaining a "short" channel. This is accomplished by forming a portion of the N+ type source region within the P body region prior to forming the trench, followed by a second implantation and diffusion of a relatively shallow extension of the N+ source region formed overlying a part of the P body region. The increased depth or doping concentration of the P body region advantageously lowers the resistance of the P body region, while the short channel lowers the on-resistance of the transistor for improved performance.

Abstract: A trenched DMOS transistor has improved device performance and production yield. During fabrication the cell trench corners, i.e. the areas where two trenches intersect, are covered on the principal surface of the integrated circuit substrate with a blocking photoresist layer during the source region implant step in order to prevent (block) a channel from forming in these corner areas. Punch-through is thereby eliminated and reliability improved, while source/drain on-resistance is only slightly increased. The blocking of the trench corners creates a cutout structure at each trench corner, whereby the source region does not extend to the trench corner, but instead the underlying oppositely-doped body region extends to the trench corner.

Abstract: A thin base oxide is disposed over both an active area and also over a field area of a substrate. A thin silicon-nitride layer is then formed over the base oxide in the active area to protect the underlying substrate from oxygen and/or water vapor during a subsequent field oxidation step. This thin nitride layer is, however, insufficiently thick to serve as a field implant mask in a subsequent field implant step. An additional low temperature oxide (LTO) layer is therefore provided over the nitride layer in the active area. The field implant step is then performed using the base oxide, the thin nitride, and the overlying LTO as a field implant mask. The boundaries of the overlying LTO define a field implant boundary. After the field implant step but before the field oxidation step, the LTO layer is removed from the top of the thin nitride layer. As a result, only the base oxide and the thin nitride layer is disposed over the active area during field oxidation.

Abstract: Non-uniformly doped regions are formed adjacent to semiconductor junctions which underlie high voltage crossovers. The non-uniformly doped regions prevent junction breakdown caused by strong electric fields. The voltage drop between a crossover and an element of an integrated circuit is spread over the non-uniformly doped region, to lessen the voltage drop between the crossover and the junction and lessen the electric field at the junction. Dopant concentrations in the non-uniformly doped region may be selected to minimize use of silicon real estate. In some embodiments, a graded dopant concentration is lightest near the junction and increases toward a circuit element being protected.

Abstract: A DMOS transistor having a trenched gate is formed in a substrate such that the P body region of the transistor may be formed heavier or deeper while still maintaining a "short" channel. This is accomplished by forming a portion of the N+ type source region within the P body region prior to forming the trench, followed by a second implantation and diffusion of a relatively shallow extension of the N+ source region formed overlying a part of the P body region. The increased depth or doping concentration of the P body region advantageously lowers the resistance of the P body region, while the short channel lowers the on-resistance of the transistor for improved performance.

Abstract: A thin base oxide is disposed over both an active area and also over a field area of a substrate. A thin silicon-nitride layer is then formed over the base oxide in the active area to protect the underlying substrate from oxygen and/or water vapor during a subsequent field oxidation step. This thin nitride layer is, however, insufficiently thick to serve as a field implant mask in a subsequent field implant step. An additional low temperature oxide (LTO) layer is therefore provided over the nitride layer in the active area. The field implant step is then performed using the base oxide, the thin nitride, and the overlying LTO as a field implant mask. The boundaries of the overlying LTO define a field implant boundary. After the field implant step but before the field oxidation step, the LTO layer is removed from the top of the thin nitride layer. As a result, only the base oxide and the thin nitride layer is disposed over the active area during field oxidation.

Abstract: A trenched DMOS transistor is fabricated using six masking steps. One masking step defines both the P+ regions and the active portions of the transistor which are masked using a LOCOS process. The LOCOS process also eliminates the poly stringer problem present in prior art structures by reducing the oxide step height. A transistor termination structure includes several field rings, each set of adjacent field rings separated by an insulated trench, thus allowing the field rings to be spaced very close together. The field rings and trenches are fabricated in the same steps as are corresponding portions of the active transistor.

Abstract: Transistor structure using a lightly doped drain (LDD) technique are disclosed. The present invention provides a reduced on-resistance in the LDD region, while retaining substantially all the high breakdown voltage advantage of the LDD technique. The advantage of the present invention is achieved by applying a non-uniform impurity design in the LDD region, increasing gradually from the gate-edge towards the contact.

Abstract: A semiconductor device, such as a MOSFET or IGT, with a deep base region having a high dopant concentration at least as high as 5.times.10.sup.19 atoms per cubic centimeter and a method of fabrication are disclosed. The novel method involves formation of the deep base region at a later stage in the fabrication and reduces the leaching of dopant from the deep base region, as well as achieving greater control over the dopant concentration in the deep base region. Further, the increased dopant concentration in the deep base region lowers the base shunt resistance of the device to provide improved electrical ruggedness. For IGTs, parasitic thyristor action is reduced.

Abstract: During fabrication of an insulated gate device, a drain-forming dopant having a relatively low diffusion coefficient is implanted along a substrate surface which overlaps the boundary between a to-be-formed vertical drain region and a to-be-formed adjacent channel region. During subsequent high temperature processing the low diffusion coefficient drain-forming dopant remains concentrated near the top surface of the substrate while other well-forming dopants, including an adjacent channel-forming dopant, which have relatively higher diffusion coefficients, diffuse to deeper regions of the substrate. The slow-diffusing drain-forming dopant retards lateral widening of the channel by the faster-diffusing channel-forming dopant just below the substrate surface to at least the depth of the channel inversion layer formed under the channel surface during device turn on.

Abstract: A process for fabricating a power IC structure which includes the following masking steps:1. CMOS P well mask2. JFET (short-channel implant) mask3. Field oxide growth mask4. Deep P+ mask5. Polysilicon mask6. DMOS P well mask7. n-/n+ mask8. Contact window mask9. Metalization mask10. Overglass mask.

Abstract: A p-type region is formed in a semiconductor body by diffusion of aluminum from an aluminum oxide source in an open tube process. Both ceramic aluminum oxide and sapphire sources are described and an inert atmosphere of argon and hydrogen provides stable results. An alternative embodiment provides both the deep diffusion characteristics of aluminum with the high surface concentration of boron by using a boron nitride wafer carrier.

Abstract: A method for forming a p-conductivity type layer in a semiconductor wafer using aluminum as a diffusion source and which can be carried out in an open diffusion tube is described. A variety of aluminum sources can be employed in an open tube. A stream of essentially oxygen-free inert gas provides transport for the dopant and prevents the entry of potentially contaminating ambient into the tube.

Abstract: A guard ring for processing a wafer of semiconductor material by thermal gradient zone melting has a beveled internal wall surface for supporting the wafer therein. The thickness of the guard ring is about twice the thickness of the wafer.