Abstract: A determination device includes an estimation circuit and a determination circuit. The estimation circuit generates estimation data by estimating input data in the n-th cycle based on the input data in cycles prior to the n-th cycle and a first generator polynomial. The determination circuit determines whether the input data and the estimation data match. The first generator polynomial is an arithmetic expression that sets the estimation data in the n-th cycle to an inverted value of the input data in (n?1)-th cycle if a logical sum of all the input data in a first period corresponding to a preset number of cycles prior to the n-th cycle is 0 or a logical product of all the input data in a second period corresponding to the preset number of cycles prior to the n-th cycle is 1, and sets the estimation data in the n-th cycle to the same value as the input data in the (n?1)-th cycle if the logical sum is not 0 and the logical product is not 1.

Abstract: A bridge chip includes a first selection circuit, a second selection circuit, and a control circuit. The first selection circuit determines an output destination of input data and an input flag indicating whether the input data is valid or invalid based on a first selection signal. The second selection circuit determines an output destination of the input data and the input flag output from the first selection circuit based on a second selection signal. The control circuit generates the first selection signal and the second selection signal, and outputs the first selection signal and the second selection signal to the first selection circuit and the second selection circuit, respectively.

Abstract: According to one embodiment, an arithmetic device includes: a first input terminal; a second input terminal; an output terminal; a first logical shifter; a second logical shifter; a third logical shifter; a first AND gate; a second AND gate; a first multiplexer; a third AND gate; a first adder; a fourth logical shifter; a second multiplexer; a second adder; a first arithmetic shifter; a second arithmetic shifter; a third arithmetic shifter; a third multiplexer; a fourth multiplexer; and a fifth multiplexer.

Abstract: According to one embodiment, an arithmetic device includes: a first input terminal; a second input terminal; an output terminal; a first logical shifter; a second logical shifter; a third logical shifter; a first AND gate; a second AND gate; a first multiplexer; a third AND gate; a first adder; a fourth logical shifter; a second multiplexer; a second adder; a first arithmetic shifter; a second arithmetic shifter; a third arithmetic shifter; a third multiplexer; a fourth multiplexer; and a fifth multiplexer.

Abstract: An equalizer control device includes a first circuit configured to, upon receipt of a data signal that has been equalized by a continuous time linear equalizer (CTLE) circuit, output a first signal related to a first number of times a waveform of the data signal crosses a threshold value or differential signals of the data signal cross each other. A second circuit is configured to count the first number during a particular time period based on the output first signal, and select one of equalization parameters to be set to the CTLE circuit based on the counted first number.

Abstract: An equalizer control device includes a first circuit configured to, upon receipt of a data signal that has been equalized by a continuous time linear equalizer (CTLE) circuit, output a first signal related to a first number of times a waveform of the data signal crosses a threshold value or differential signals of the data signal cross each other. A second circuit is configured to count the first number during a particular time period based on the output first signal, and select one of equalization parameters to be set to the CTLE circuit based on the counted first number.

Abstract: According to one embodiment, an electronic device executes decision feedback-type equalization for input data using a tap coefficient while updating the tap coefficient. The electronic device includes a first memory cyclically receiving a tap coefficient, holing the tap coefficient received, and cyclically outputting the tap coefficient held, and a second memory receiving the tap coefficient cyclically output from the first memory and holding the tap coefficient received. The tap coefficient cyclically output from the first memory is delayed by at least one cycle than the tap coefficient cyclically received by the first memory. The tap coefficient held in the second memory is used for the decision feedback-type equalization in a no-signal period in which no input data exist.

Abstract: According to one embodiment, ao electronic device executes decision feedback-type equalization for input data using a tap coefficient while updating the tap coefficient. The electronic device includes a first memory cyclically receiving a tap coefficient, holing the tap coefficient received, and cyclically outputting the tap coefficient held, and a second memory receiving the tap coefficient cyclically output from the first memory and holding the tap coefficient received. The tap coefficient cyclically output from the first memory is delayed by at least one cycle than the tap coefficient cyclically received by the first memory. The tap coefficient held in the second memory is used for the decision feedback-type equalization in a no-signal period in which no input data exist.

Abstract: A parallel-serial converter circuit has a frequency divider configured to generate a frequency-divided signal by dividing a frequency of a reference clock signal by a dividing ratio depending on a logic of a speed control signal, a timing pulse generator configured to generate a timing pulse signal based on the frequency-divided signal, a load signal generator configured to generate a load signal based on the speed control signal and the timing pulse signal, a bit clock generator configured to generate a bit clock signal based on the speed control signal and the timing pulse signal, and a parallel-serial converter configured to newly load the parallel data in synchronization with the load signal and convert the loaded parallel data into serial data in synchronization with the bit clock signal.

Abstract: A parallel-serial converter circuit has a frequency divider configured to generate a frequency-divided signal by dividing a frequency of a reference clock signal by a dividing ratio depending on a logic of a speed control signal, a timing pulse generator configured to generate a timing pulse signal based on the frequency-divided signal, a load signal generator configured to generate a load signal based on the speed control signal and the timing pulse signal, a bit clock generator configured to generate a bit clock signal based on the speed control signal and the timing pulse signal, and a parallel-serial converter configured to newly load the parallel data in synchronization with the load signal and convert the loaded parallel data into serial data in synchronization with the bit clock signal.

Abstract: An illumination unit of the present invention includes a tabular light guide plate having a light emitting surface for emitting light coming from an LED as planar light, wherein a recessed portion is formed in the opposite surface of the light emitting surface of the light guide plate, and wherein the LED is provided in the recessed portion so that the optical axis of the LED becomes parallel to the light emitting surface of the light guide plate. Then, a dimming pattern is provided at a location corresponding to the LED of the light emitting surface of the light guide plate, and the dimming pattern includes a main portion covering the LED on the light emitting surface side, and protrusions radially extending toward a light emitting direction of the LED around the LED.

Abstract: An illumination unit includes an LED and a tabular light guide plate having a light emitting surface for emitting light from the LED as planar light, wherein a recessed portion is formed in the opposite surface of the tight emitting surface of the light guide plate, and wherein the LED is provided in the recessed portion so that the optical axis of the LED becomes parallel to the light emitting surface of the light guide plate. Further, a plurality of LEDs are arranged along the longer direction of the recessed portion, a dimming pattern is provided at a location corresponding to each of a plurality of LED of the light emitting surface of the light guide plate, and the shape or the size of the dimming pattern is varied with a location on the light emitting surface of the light guide plate.

Abstract: An illumination unit includes LEDs and a tabular light guide plate having a light emitting surface for emitting light from the LEDs as planar light, wherein a recessed portion is formed in the opposite surface of the light emitting surface of the light guide plate, and the LED is provided in the recessed portion so that the optical axis of the LED becomes parallel to the light emitting surface of the light guide plate. Here, a dimming pattern is provided at a location corresponding to the LED of the light emitting surface of the light guide plate, and furthermore a first light guide pattern is provided on the light emitting surface of the light guide plate and a second light guide pattern is provided on a rear surface that is a reflective surface.

Abstract: An illumination unit of the present invention includes a tabular light guide plate having a light emitting surface for emitting light coming from an LED as planar light, wherein a recessed portion is formed in the opposite surface of the light emitting surface of the light guide plate, and wherein the LED is provided in the recessed portion so that the optical axis of the LED becomes parallel to the light emitting surface of the light guide plate. Then, a dimming pattern is provided at a location corresponding to the LED of the light emitting surface of the light guide plate, and the dimming pattern includes a main portion covering the LED on the light emitting surface side, and protrusions radially extending toward a light emitting direction of the LED around the LED.

Abstract: An illumination unit includes LEDs and a tabular light guide plate having a light emitting surface for emitting light from the LEDs as planar light, wherein a recessed portion is formed in the opposite surface of the light emitting surface of the light guide plate, and the LED is provided in the recessed portion so that the optical axis of the LED becomes parallel to the light emitting surface of the light guide plate. Here, a dimming pattern is provided at a location corresponding to the LED of the light emitting surface of the light guide plate, and furthermore a first light guide pattern is provided on the light emitting surface of the light guide plate and a second light guide pattern is provided on a rear surface that is a reflective surface.

Abstract: An illumination unit includes an LED and a tabular light guide plate having a light emitting surface for emitting light from the LED as planar light, wherein a recessed portion is formed in the opposite surface of the tight emitting surface of the light guide plate, and wherein the LED is provided in the recessed portion so that the optical axis of the LED becomes parallel to the light emitting surface of the light guide plate. Further, a plurality of LEDs are arranged along the longer direction of the recessed portion, a dimming pattern is provided at a location corresponding to each of a plurality of LED of the light emitting surface of the light guide plate, and the shape or the size of the dimming pattern is varied with a location on the light emitting surface of the light guide plate.

Abstract: An illumination device for guiding light rays from a light-emitting diode (LED) module toward a light guide plate to thereby perform planar illumination is disclosed. The illumination device includes a printed circuit board with a plurality of LED elements attached thereto. The circuit board has two or more positioning bosses which are attached in the same process as that of the LEDs. While letting the positioning bosses be tightly coupled with corresponding holes provided in the light guide plate, the circuit board and the light guide plate are adhered and fixed together, thereby accurately retaining the positional relationship between the LEDs and the light guide plate.

Abstract: According to the present invention, the amount of usage of a heat conductive member for fixing a self-luminous flat display panel to a metallic chassis member disposed at the back of the display panel is reduced in the thickness direction as well as in the surface direction. The invention further provides a technique for efficiently radiating heat from the display panel, suppressing cost increase. To this end, in the invention, the heat conductive member is a hot-melt adhesive having adhesion at room temperature and filled with a heat conduction imparting agent, and the display panel is fixed to the chassis member by a plurality of heat conducting sections of the heat conductive member formed discretely ranging from 0.3 to 0.8 mm in thickness.

Abstract: A projection type display apparatus includes a housing having a first side on which an air intake opening is arranged and a second side on which an air exhaust opening is arranged, a light source for supplying light, and a light valve device which modulates the light output from the light source. A first fan is provided which draws air from the air intake opening into the housing, and a first ventilation path is coupled with the air intake opening so as to lead air flow from the air intake opening toward a lower portion of the light valve. A second ventilation path is formed from the lower portion of the light valve to an upper portion of the light valve, and a second fan is provided which draws out air flowing from the second ventilation path through the air exhaust opening to outside of the housing.