Patents by Inventor Mikio Takagi
Mikio Takagi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20070124713Abstract: A navigation system for easily determining defective positions is provided. In the case of CAD navigation to defective positions, logical information for indicating defective positions is created in a CAD format, instead of CAD data of physical information indicating circuit design. Specifically, by attaching marks such as rectangles, characters, or lines, to an electron microscope image with software, quick navigation is performed with required minimum information. By using created CAD data, re-navigation with the same equipment and CAD navigation to heterogeneous equipment are performed.Type: ApplicationFiled: October 20, 2006Publication date: May 31, 2007Inventors: Tohru Ando, Tsutomu Saito, Yasuhiko Nara, Mikio Takagi, Koichi Takauchi
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Publication number: 20050244722Abstract: In a halftone phase shift mask blank comprising a substrate, a light absorbing film, and a phase shifter film, the light absorbing film contains a metal element of Group 4A in a distribution having a higher metal element content in an upper region than in a lower region. Also provided is a halftone phase shift mask blank comprising a transparent substrate and a halftone phase shift film of a single layer or multiple layers having a preselected phase difference and transmittance, wherein at least one layer of the halftone phase shift film contains at least 90 atom % of silicon and a plurality of metal elements, typically Mo and Zr or Hf.Type: ApplicationFiled: March 30, 2005Publication date: November 3, 2005Applicants: Shin-Etsu Chemical Co., Ltd., Toppan Printing Co., Ltd.Inventors: Kimihiro Okada, Masahide Iwakata, Takashi Haraguchi, Mikio Takagi, Yuichi Fukushima, Hiroki Yoshikawa, Toshinobu Ishihara, Satoshi Okazaki, Yukio Inazuki, Tadashi Saga
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Publication number: 20050130451Abstract: Disclosed are a method and an apparatus for processing a wafer in manufacturing a semiconductor device and a method and an apparatus for etching a material formed on the wafer, wherein first and second cooling parts adjust an ambient temperature near a plurality of wafers to a first temperature, the wafers are processed by introducing a reaction gas at the first temperature, then, a heating part rapidly raises the temperature of the atmosphere near the wafers from the first temperature to the second temperature to partially separate by-products produced during the processing, the second temperature is maintained to separate most of the by-products from the wafers, and the processing steps are implemented in-situ within the same space. Accordingly, a native oxide layer formed on several wafers can be etched and the reaction by-products can be removed in-situ in the same chamber so productivity is improved.Type: ApplicationFiled: February 7, 2005Publication date: June 16, 2005Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kwang-Myung Lee, Mikio Takagi, Jae-Hyuk An, Seung-Ki Chae, Jea-Wook Kim
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Patent number: 6869500Abstract: Disclosed are a method and an apparatus for processing a wafer in manufacturing a semiconductor device and a method and an apparatus for etching a material formed on the wafer, wherein first and second cooling parts adjust an ambient temperature near a plurality of wafers to a first temperature, the wafers are processed by introducing a reaction gas at the first temperature, then, a heating part rapidly raises the temperature of the atmosphere near the wafers from the first temperature to the second temperature to partially separate by-products produced during the processing, the second temperature is maintained to separate most of the by-products from the wafers, and the processing steps are implemented in-situ within the same space. Accordingly, a native oxide layer formed on several wafers can be etched and the reaction by-products can be removed in-situ in the same chamber so productivity is improved.Type: GrantFiled: September 9, 2002Date of Patent: March 22, 2005Assignee: Samsung Electronics Co., Ltd.Inventors: Kwang-Myung Lee, Mikio Takagi, Jae-Hyuk An, Seung-Ki Chae, Jea-Wook Kim
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Patent number: 6867147Abstract: A method of removing native oxide film from contact holes of a semiconductor device by using a microwave-excited reactive gas. The method increases throughput. Reactive gas is introduced substantially horizontally into the reactor (20) by way of a chamber (5, 22) arranged as an extension thereof in the vertical direction of the reactor (20) and showing an internal pressure higher than that of the reactor, while the plurality of semiconductor silicon wafers (10) that are arranged in the vertical direction and held to temperature not higher than 323 K are being rotated, and subsequently said reactor is heated (30) to above 373 K.Type: GrantFiled: March 28, 2001Date of Patent: March 15, 2005Assignee: F.T.L. Co., LTDInventor: Mikio Takagi
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Patent number: 6793734Abstract: An assembly of heating furnace and semiconductor wafer-holding jig. This assembly includes a furnace body made of refractory or heat insulting material; a heater disposed around the inner side surface of the furnace body; a reaction chamber which forms a uniform heating zone; and a wafer-holding jig. The wafer-holding jig is capable of holding the wafer and advancing and retracting the wafer in the uniform heating region along the longitudinal direction of the furnace body. The front surface of the semiconductor wafer to be heat-treated is substantially in parallel with the surface of the heater. The assembly of the invention can be used in rapid thermal processing and the footprint of the heating furnace can be reduced.Type: GrantFiled: July 25, 2002Date of Patent: September 21, 2004Assignees: F.T.L. Co., Ltd., Topco Scietific Co., Ltd.Inventor: Mikio Takagi
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Publication number: 20040175878Abstract: An assembly of heating furnace and semiconductor wafer-holding jig. This assembly includes a furnace body made of refractory or heat insulting material; a heater disposed around the inner side surface of the furnace body; a reaction chamber which forms a uniform heating zone; and a wafer-holding jig. The wafer-holding jig is capable of holding the wafer and advancing and retracting the wafer in the uniform heating region along the longitudinal direction of the furnace body. The front surface of the semiconductor wafer to be heat-treated is substantially in parallel with the surface of the heater. The assembly of the invention can be used in rapid thermal processing and the footprint of the heating furnace can be reduced.Type: ApplicationFiled: March 12, 2004Publication date: September 9, 2004Inventor: Mikio Takagi
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Patent number: 6686259Abstract: In a method for manufacturing a solid state image pick up device capable of improving gettering efficiency a semiconductor substrate having a front side on which a solid state image pick-up device may be formed, and a rear side opposite to the front side is provided. Subsequently, a polysilicon layer including impurities for gettering having a predetermined concentration is formed on the rear side of the semiconductor substrate. Next, a predetermined thickness of the polysilicon layer including the impurities for gettering is oxidized, and the impurities for gettering are condensed into the reduced polysilicon layer.Type: GrantFiled: November 27, 2001Date of Patent: February 3, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-sik Park, Mikio Takagi, Jae-heon Choi, Sang-il Jung, Jun-taek Lee
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Publication number: 20030204432Abstract: A method provides a user with access to resources associated with a life or work event by enabling the user to perform certain operations, including specifying a list of one or more tasks corresponding to the event, specifying one or more resources associated with each task, indicating a task order (including an indication of whether two or more tasks in the task list are to be performed in an order-dependent or in an order-independent manner), and formatting the task list into a presentation format. A system with user interface controls enables a user to perform certain operations, including designating an event, generating a list of tasks associated with the event, and specifying an order for performance of the tasks in the task list that may be followed in processing an instance of the event.Type: ApplicationFiled: April 30, 2002Publication date: October 30, 2003Inventors: Martin Botscheck, Udo Waibel, Mirjam Sonnleithner, Monty Gray, Wolfram Hepp, Martin Zurmuehl, Heiko Schultze, Mikio Takagi, Wolfgang Kuhn, Herbert Penzkofer
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Publication number: 20030204429Abstract: A system with user interface controls, a build component, a runtime component, and a workflow engine enables a user to specify an event definition, create an event instance based on the event definition, and process the event instance. The event definition may include a list of tasks corresponding to a life or work event, a specification of resources associated with each task, and a task order. The user may deselect optional tasks, specify participants who are to collaborate in the event, and otherwise personalize the event instance. The user processes the event instance by selecting tasks in accordance with the task order. The system provides access to the resources associated with each task, and allows the user to mark tasks as completed, and to store and monitor the progress of the event instance. Multiple event instances that are created from the same event definition can be processed independently.Type: ApplicationFiled: May 31, 2002Publication date: October 30, 2003Inventors: Martin Botscheck, Udo Waibel, Mirjam Sonnleithner, Monty Gray, Wolfram Hepp, Martin Zurmuehl, Heiko Schultze, Mikio Takagi, Wolfgang Kuhn, Herbert Penzkofer
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Publication number: 20030186517Abstract: A vertical single wall reaction tube type batch processing furnace can reduce the generation of particles. A method of removing native oxide film by fluoride gas can enhance the efficiency of utilization of gas. A method of exciting reaction gas by a catalyst at high temperature can be applied to a batch processing. A method of exciting reaction gas by a catalyst utilizes an oxidizing agent and gas other than an oxidizing agent. The flow rate of gas in the gas injection pipe and that of gas in the exhaust pipe are made to be substantially equal to each other. The gap between two adjacent wafers is made greater than the mean free path of gas. The oxidizing agent is dissociated by a catalyst of Ir, V or Kanthal while the gas other than the oxidizing agent is dissociated by a catalyst of W.Type: ApplicationFiled: March 31, 2003Publication date: October 2, 2003Inventor: Mikio Takagi
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Publication number: 20030148621Abstract: A method of removing native oxide film from contact holes of a semiconductor device by using a microwave-excited reactive gas. The method increases throughput. Reactive gas is introduced substantially horizontally into the reactor (20) by way of a chamber (5, 22) arranged as an extension thereof in the vertical direction of the reactor (20) and showing an internal pressure higher than that of the reactor, while the plurality of semiconductor silicon wafers (10) that are arranged in the vertical direction and held to temperature not higher than 323 K are being rotated, and subsequently said reactor is heated (30) to above 373 K.Type: ApplicationFiled: December 11, 2002Publication date: August 7, 2003Inventor: Mikio Takagi
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Publication number: 20030060030Abstract: Disclosed are a method and an apparatus for processing a wafer in manufacturing a semiconductor device and a method and an apparatus for etching a material formed on the wafer, wherein first and second cooling parts adjust an ambient temperature near a plurality of wafers to a first temperature, the wafers are processed by introducing a reaction gas at the first temperature, then, a heating part rapidly raises the temperature of the atmosphere near the wafers from the first temperature to the second temperature to partially separate by-products produced during the processing, the second temperature is maintained to separate most of the by-products from the wafers, and the processing steps are implemented in-situ within the same space. Accordingly, a native oxide layer formed on several wafers can be etched and the reaction by-products can be removed in-situ in the same chamber so productivity is improved.Type: ApplicationFiled: September 9, 2002Publication date: March 27, 2003Inventors: Kwang-Myung Lee, Mikio Takagi, Jae-Hyuk An, Seung-Ki Chae, Jea-Wook Kim
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Publication number: 20030031974Abstract: An assembly of heating furnace and semiconductor wafer-holding jig. This assembly includes a furnace body made of refractory or heat insulting material; a heater disposed around the inner side surface of the furnace body; a reaction chamber which forms a uniform heating zone; and a wafer-holding jig. The wafer-holding jig is capable of holding the wafer and advancing and retracting the wafer in the uniform heating region along the longitudinal direction of the furnace body. The front surface of the semiconductor wafer to be heat-treated is substantially in parallel with the surface of the heater. The assembly of the invention can be used in rapid thermal processing and the footprint of the heating furnace can be reduced.Type: ApplicationFiled: July 25, 2002Publication date: February 13, 2003Inventor: Mikio Takagi
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Publication number: 20020127762Abstract: In a method for manufacturing a solid state image pick up device capable of improving gettering efficiency a semiconductor substrate having a front side on which a solid state image pick-up device may be formed, and a rear side opposite to the front side is provided. Subsequently, a polysilicon layer including impurities for gettering having a predetermined concentration is formed on the rear side of the semiconductor substrate. Next, a predetermined thickness of the polysilicon layer including the impurities for gettering is oxidized, and the impurities for gettering are condensed into the reduced polysilicon layer.Type: ApplicationFiled: November 27, 2001Publication date: September 12, 2002Applicant: Samsung Electronics Co., Ltd.Inventors: Sang-sik Park, Mikio Takagi, Jae-heon Choi, Sang-il Jung, Jun-taek Lee
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Patent number: 6248672Abstract: In a method for producing a semiconductor device using a dual tube reactor, inert gas is fed into the vertical reaction-tube, a reaction gas is introduced into the vertical reaction-tube, the inert gas is exhausted through the annular channel formed between the inner tube and the outer tube at a bottom portion of the vertical reaction-tube; and, a wafer is heat treated in the vertical reaction-tube by means of a heating furnace. In order to decrease the number and size of the particles, the wafer is displaced upward and then positioned at a level substantially the same as or above the top end of the inner tube, and the reaction gas is introduced into the vertical reaction-tube at or above the position of the wafer. Furthermore, the inert gas is caused to flow from a bottom portion of the inner tube toward the wafer positioned as above. As a result, inflow of the reaction gas into the inner tube is impeded, and the generation of particles there can be lessened.Type: GrantFiled: May 13, 1999Date of Patent: June 19, 2001Assignee: F.T.L. Co., Ltd.Inventor: Mikio Takagi
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Patent number: 6204194Abstract: The film growth speed of a conventional vertical heating method, such as SiO2 film, polycrystalline Si film or the like of a semiconductor device, is enhanced by means of discharging and sucking the reaction gas onto and from the Si wafers placed horizontally in the vertical furnace. The wafers are rotated and the wafer-distance is set at 5 mm or more.Type: GrantFiled: January 15, 1999Date of Patent: March 20, 2001Assignee: F.T.L. Co., Ltd.Inventor: Mikio Takagi
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Patent number: 6159873Abstract: In a RTP (rapid Thermal Processing) of a large-diameter semiconductor wafer using a hot-wall type heating furnace, the temperature distribution of the wafer surface is made uniform by means of preliminarily heating a thermal storage plate(s) to a heat-treating temperature, and, then positioning the wafer between a pair of the thermal storage plates or in the direct proximity of a thermal storage plate. The wafer may be brought into contact with the thermal storage plate. The wafer is thus heated rapidly heated to the heat treating temperature.Type: GrantFiled: March 29, 1996Date of Patent: December 12, 2000Assignee: F.T.L. Co., Ltd.Inventor: Mikio Takagi
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Patent number: 6077573Abstract: A method of forming a microelectronic device includes the step of forming an impurity doped amorphous silicon layer on a microelectronic substrate using plasma-enhanced chemical vapor deposition. The impurity doped amorphous silicon layer is patterned so that portions of the microelectronic substrate are exposed adjacent the patterned amorphous silicon layer. A hemispherical grained silicon layer is then formed on the patterned amorphous silicon layer. Moreover, the step of forming the impurity doped amorphous silicon layer can be performed at a temperature of 400.degree. C. or less.Type: GrantFiled: May 22, 1998Date of Patent: June 20, 2000Assignee: Samsung Electronics Co., Ltd.Inventors: Young-sun Kim, Sang-hyeop Lee, Seung-hwan Lee, Young-wook Park, Mikio Takagi
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Patent number: 5972116Abstract: In a method for producing a semiconductor device using a dual tube reactor, inert gas is fed into the vertical reaction-tube, a reaction gas is introduced into the vertical reaction-tube, the inert gas is exhausted through the annular channel formed between the inner tube and the outer tube at a bottom portion of the vertical reaction-tube; and, a wafer is heat treated in the vertical reaction-tube by means of a heating furnace. In order to decrease the number and size of the particles, the wafer is displaced upward and then positioned at a level substantially the same as or above the top end of the inner tube, and the reaction gas is introduced into the vertical reaction-tube at or above the position of the wafer. Furthermore, the inert gas is caused to flow from a bottom portion of the inner tube toward the wafer positioned as above. As a result, inflow of the reaction gas into the inner tube is impeded, and the generation of particles there can be lessened.Type: GrantFiled: December 28, 1995Date of Patent: October 26, 1999Assignee: F.T.I. Co., Ltd.Inventor: Mikio Takagi