Abstract: Compounds having formula (I), and enantiomers, and diastereomers, stereoisomers, pharmaceutically acceptable salts thereof, are useful as kinase modulators, including RIPK1 modulation. All the variables are as defined herein.

Abstract: A method includes providing a structure. The structure includes an active region having a channel region and a source/drain region adjacent to the channel region, a gate structure over the channel region, a source/drain feature over the source/drain region, a contact etch stop layer (CESL) over the source/drain feature, and an interlayer dielectric (ILD) layer over the CESL. The method further includes forming a trench in the CESL and the ILD layer to expose the source/drain feature, providing a metal precursor and a phosphorus source in the trench, thereby forming a metal phosphide layer over the source/drain feature, forming a silicide layer on the metal phosphide layer, and forming a metal fill layer in the trench.

Abstract: The present invention provides compounds, compositions thereof, and methods of using the MK2 inhibitors of the Formula:

Abstract: An adhesive tape that includes: a first adhesive layer defining an upper surface of the tape; a second adhesive layer defining a lower surface of the tape; and a reinforcement layer (or first and second reinforcement layers) and a thermally activated layer between the first adhesive layer and the second adhesive layer. The thermally activated layer is a thermoplastic polymer layer. The thermoplastic layer may be made of ethylene-vinyl acetate copolymer, modified polyolefin, ethylene acrylic acid copolymer, ethylene terpolymer, polyamide copolymer, poly(trans-1,4-isoprene), polyethylene oxide, or a combination thereof. Further, the thermoplastic layer may exhibit a melting point from 60° C. to 150° C. and may have a molecular weight from 1,000 to 1,000,000.

Abstract: The present disclosure provides a polyamide composite, including the following components in parts by weight: 77.2 parts to 94.8 parts of PAXI/XT, 5 parts to 20 parts of a semi-crystalline polyamide, and 0.2 part to 0.8 part of a powder of organosilicon elastomer including a methacryloxy functional group. The semi-crystalline polyamide is at least one selected from the group consisting of PA66, PA610, PA612, PA106, PA1010, and PA1012, and the PAXI/XT is a copolymer of an aliphatic diamine X, isophthalic acid I, and terephthalic acid T. The polyamide composite has advantages such as high light transmittance, high haze (excellent light-scattering performance), and prominent chemical resistance, and is suitable for the preparation of navigation lights for plant protection drones.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base. The semiconductor device structure includes a first multilayer stack over the base. The first multilayer stack includes a first channel layer and a second channel layer over and spaced apart from the first channel layer. The semiconductor device structure includes a gate stack over the substrate. The gate stack wraps around the first multilayer stack. The semiconductor device structure includes an inner spacer layer between the second channel layer and the first channel layer and between the first channel layer and the base. The semiconductor device structure includes a bottom spacer over the base. The semiconductor device structure includes a first source/drain structure over the bottom spacer and connected to the second channel layer.

Abstract: A semiconductor device includes a first epitaxial source/drain feature, a second epitaxial source/drain feature, two or more semiconductor layers and at least one dielectric spacer. The two or more semiconductor layers are electrically connected between the first epitaxial source/drain feature and the second epitaxial source/drain feature. The dielectric spacer is located between the two or more semiconductor layers, the dielectric spacer surrounds two opposite sides of the first epitaxial source/drain feature and the second epitaxial source/drain feature, and an interface between the dielectric spacer and each of the two opposite sides is a plane.

Abstract: Systems, computer program products, and methods are described herein for component-level threat assessment in a computing environment. The present disclosure is configured to capture state information associated with a computing environment; determine correlation measures for the components in the computing environment based on at least the state information; determine threat vectors associated with the components; determine mitigation protocols to be implemented on the components in response to an incidence of the threat vectors on the components; determine a first sequence in which the mitigation protocols are to be implemented based on at least the correlation measures for the components; and implement the mitigation protocols on the components in the first sequence to reduce a propagation effect of the threat vectors across the computing environment.

Abstract: The invention discloses an in situ polymerized flame retardant, derived from the following monomers: a diacid monomer A: where A1 is terephthalic acid, A2 is a phosphorus aromatic ring-containing reactive flame-retardant diacid monomer, A1+A2=100 mol %, A1=50 to 90 mol %, A2=10 to 50 mol %; and a diamine monomer B: one or more of diamine monomers containing 4 to 36 carbon atoms. In the present invention, a novel flame retardant is obtained by in situ polymerization of the phosphorus aromatic ring-containing reactive flame-retardant diacid monomers in semi-aromatic polyamide oligomers, which has advantages of no precipitation in the semi-aromatic polyamide and no influence on other properties of the semi-aromatic polyamide and has an excellent flame-retardant property.

Abstract: The present application provides a pavement technical condition detection method and device based on a three-dimensional contour. The method includes: acquiring three-dimensional contour data and grayscale data of a pavement on the basis of a line scanning three-dimensional measurement sensor; preprocessing the three-dimensional contour data and the grayscale data, where the preprocessing includes performing three-dimensional modeling according to the three-dimensional contour data to acquire three-dimensional modeling data and correcting the grayscale data; and extracting a key contour of each cross section in the three-dimensional modeling data, and performing pavement technical condition index detection on the pavement according to the three-dimensional modeling data, the key contour, and the corrected grayscale data to acquire a technical condition index of the pavement.

Abstract: Interposers for semiconductor packages including photonic components, such as an optical waveguide and/or an integrated circuit (IC) photonic die, integrated into the interposer. The interposer includes a substrate, a redistribution structure over the substrate, where the redistribution structure includes a plurality of conductive features in a dielectric material, and an optical waveguide located over and/or within the substrate. The optical waveguide includes a core material surrounded by a cladding material, where the core material has an index of refraction that is greater than an index of refraction of the cladding material, and the optical waveguide is configured to transmit optical signals through the interposer to and/or from an IC photonic die electrically coupled to an IC electronic die that provides an interface between electronic and photonic components of the semiconductor package.

Abstract: Access entitlement decisioning for a network-based application occurs dynamically at the time of access request based on current scenario indicators. In addition to determining whether a user should be granted access/entitlement, in certain instances, the current scenario indicators are relied upon to determine the level of entitlement/access (i.e., less or more than standard access) and the period for enforcing the determined access/entitlement. The current scenario indicators may be associated with the user, the application and/or the computing environment and are indicative of a heightened awareness for the occurrence of potential deceptive events or the likelihood for inefficiencies in use of the application and/or computing environment.

Abstract: A remote reconfiguration system for an Internet of Things (IoT) intelligent sensing terminal includes: a controlled terminal with a field programmable gate array (FPGA); and a remote control unit connected to the controlled terminal and a control device; where the remote control unit is configured to receive control information sent by the control device, process the control information and send the processed control information to the FPGA, such that the FPGA performs remote local autonomous reconfiguration based on the preprocessed control information. The system resolves problems that a traditional IoT terminal cannot realize remote control and cannot follow functional requirements to perform local autonomous reconfiguration, and has better versatility and expandability.

Abstract: The present disclosure provides a semiconductor device and a method of forming the same. A method according one embodiment of the present disclosure includes forming a first stack over a substrate and a second stack over the first stack. The first stack includes semiconductor layers interleaved by dielectric layers. The second stack includes channel layers interleaved by sacrificial layers. The method also includes patterning the second stack to form a fin-shape structure, recessing a portion of the fin-shape structure to form a recess exposing a top surface of the first stack, epitaxially growing an epitaxial feature directly from the top surface of the first stack, removing the sacrificial layers to release the channel layers, and forming a gate structure wrapping around each of the channel layers.

Abstract: Various embodiments of the present application are directed towards a bipolar selector having independently tunable threshold voltages, as well as a memory cell comprising the bipolar selector and a memory array comprising the memory cell. In some embodiments, the bipolar selector comprises a first unipolar selector and a second unipolar selector. The first and second unipolar selectors are electrically coupled in parallel with opposite orientations and may, for example, be diodes or some other suitable unipolar selectors. By placing the first and second unipolar selectors in parallel with opposite orientations, the first unipolar selector independently defines a first threshold voltage of the bipolar selector and the second unipolar selector independently defines a second threshold voltage of the bipolar selector. As a result, the first and second threshold voltages can be independently tuned by adjusting parameters of the first and second unipolar selectors.

Abstract: The present disclosure provides a semiconductor device and a method of forming the same. A method according one embodiment of the present disclosure includes forming a first stack over a substrate and a second stack over the first stack. The first stack includes semiconductor layers interleaved by dielectric layers. The second stack includes channel layers interleaved by sacrificial layers. The method also includes patterning the second stack to form a fin-shape structure, recessing a portion of the fin-shape structure to form a recess exposing a top surface of the first stack, epitaxially growing an epitaxial feature directly from the top surface of the first stack, removing the sacrificial layers to release the channel layers, and forming a gate structure wrapping around each of the channel layers.

Abstract: Semiconductor devices including backside capacitors and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure, the front-side interconnect structure including a front-side conductive line; a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a backside conductive line, the backside conductive line having a line width greater than a line width of the front-side conductive line; and a first capacitor structure coupled to the backside interconnect structure.

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes an operative memory device. A regulating access apparatus is coupled to the operative memory device. The regulating access apparatus includes one or more regulating magnetic tunnel junction (MTJ) devices respectively having a regulating free layer, a regulating dielectric barrier layer, and a regulating pinned layer separated from the regulating free layer by the regulating dielectric barrier layer. The regulating pinned layer continuously extends between opposing outermost sidewalls of the regulating dielectric barrier layer.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first fin active region of a first semiconductor material disposed within the first region, oriented in a first direction, wherein the first fin active region has a <100> crystalline direction along the first direction; and a second fin active region of a second semiconductor material disposed within the second region and oriented in the first direction, wherein the second fin active region has a <110> crystalline direction along the first direction.

Abstract: Various embodiments of the present application are directed towards a bipolar selector having independently tunable threshold voltages, as well as a memory cell comprising the bipolar selector and a memory array comprising the memory cell. In some embodiments, the bipolar selector comprises a first unipolar selector and a second unipolar selector. The first and second unipolar selectors are electrically coupled in parallel with opposite orientations and may, for example, be diodes or some other suitable unipolar selectors. By placing the first and second unipolar selectors in parallel with opposite orientations, the first unipolar selector independently defines a first threshold voltage of the bipolar selector and the second unipolar selector independently defines a second threshold voltage of the bipolar selector. As a result, the first and second threshold voltages can be independently tuned by adjusting parameters of the first and second unipolar selectors.