Patents by Inventor Min Cao

Min Cao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210162427
    Abstract: Disclosed is an underground coal preparation process adopting a water medium, comprising: feeding exploited raw coal into a ?25 mm raw coal classifying screen for screening; performing dry coal preparation on a classifying screen oversize product with a particle size greater than 25 mm and feeding a classifying screen undersize product with a particle size less than 25 mm into a special underground compact jigging machine for sorting to obtain jigging machine overflow clean coal, jigging middling coal and jigging gangue; screening and dewatering the jigging machine overflow clean coal to obtain a clean coal product, and screening and dewatering the jigging middling coal to obtain a middling coal product, sorting slime water to be sorted and generated during sorting to obtain coarse clean coal slime and coarse middling coal slime, and performing circulating water treatment on a final liquid.
    Type: Application
    Filed: April 22, 2019
    Publication date: June 3, 2021
    Applicant: CHINA UNIVERSITY OF MINING AND TECHNOLOGY
    Inventors: Xiahui GUI, Min LIU, Yaowen XING, Yangchao XIA, Yijun CAO, Jiaqian LUO, Peikun LIU, Zhigang WANG
  • Patent number: 10991756
    Abstract: Various embodiments of the present application are directed towards a bipolar selector having independently tunable threshold voltages, as well as a memory cell comprising the bipolar selector and a memory array comprising the memory cell. In some embodiments, the bipolar selector comprises a first unipolar selector and a second unipolar selector. The first and second unipolar selectors are electrically coupled in parallel with opposite orientations and may, for example, be diodes or some other suitable unipolar selectors. By placing the first and second unipolar selectors in parallel with opposite orientations, the first unipolar selector independently defines a first threshold voltage of the bipolar selector and the second unipolar selector independently defines a second threshold voltage of the bipolar selector. As a result, the first and second threshold voltages can be independently tuned by adjusting parameters of the first and second unipolar selectors.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: April 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Chih Lai, Chung-Te Lin, Min Cao, Randy Osborne
  • Publication number: 20210098625
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first gate stack and a second gate stack over a substrate. The substrate has a base, a first fin structure, and a second fin structure over the base, the second fin structure is wider than the first fin structure. The method includes partially removing the first fin structure, which is not covered by the first gate stack, and the second fin structure, which is not covered by the second gate stack. The method includes forming an inner spacer layer over the first fin structure, which is not covered by the first gate stack. The method includes forming a first stressor and a second stressor respectively over the inner spacer layer and the second fin structure, which is not covered by the second gate stack.
    Type: Application
    Filed: September 27, 2019
    Publication date: April 1, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Wei TSAI, Yu-Xuan HUANG, Kuan-Lun CHENG, Chih-Hao WANG, Min CAO, Jung-Hung CHANG, Lo-Heng CHANG, Pei-Hsun WANG, Kuo-Cheng CHIANG
  • Publication number: 20210066469
    Abstract: The present disclosure provides a method of forming a semiconductor device including an nFET structure and a pFET structure where each of the nFET and pFET structures include a semiconductor substrate and a gate trench. The method includes depositing an interfacial layer in each gate trench; depositing a first metal oxide layer over the interfacial layer; removing the first metal oxide layer from the pFET structure; depositing a ferroelectric layer in each gate trench; depositing a second metal oxide layer over the ferroelectric layer; removing the second metal oxide layer from the nFET structure; and depositing a gate electrode in each gate trench.
    Type: Application
    Filed: June 8, 2020
    Publication date: March 4, 2021
    Inventors: Min Cao, Pei-Yu Wang, Sai-Hooi Yeong, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20210057580
    Abstract: A semiconductor device including a 2D material layer disposed between a gate electrode and a substrate and a method of forming the same are disclosed. In an embodiment, a device includes a ferroelectric dielectric layer disposed over and in contact with a semiconductor substrate, the ferroelectric dielectric layer including a 2D material; a gate electrode disposed over the ferroelectric dielectric layer; and source/drain regions disposed on opposite sides of the gate electrode.
    Type: Application
    Filed: August 23, 2019
    Publication date: February 25, 2021
    Inventors: Chi On Chui, Sai-Hooi Yeong, Syun-Ming Jang, Min Cao
  • Publication number: 20210057273
    Abstract: Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a second contact feature over the first contact feature, a barrier layer between the second dielectric layer and the second contact feature, and a liner between the barrier layer and the second contact feature. An interface between the first contact feature and the second contact feature includes the liner but is free of the barrier layer.
    Type: Application
    Filed: August 22, 2019
    Publication date: February 25, 2021
    Inventors: Hsin-Ping Chen, Ming-Han Lee, Shin-Yi Yang, Yung-Hsu Wu, Chia-Tien Wu, Shau-Lin Shue, Min Cao
  • Publication number: 20200348932
    Abstract: A memory control system includes a memory interface, a microcontroller, and a sequence processing unit. The memory interface circuit receives a memory operation command and generates a plurality of operation instructions according to the memory operation command. The microcontroller is coupled to the memory interface circuit . The microcontroller receives the plurality of operation instructions and generates a plurality of task instructions according a scheduling algorithm through a predetermined protocol. The sequence processing unit is coupled to the microcontroller. The sequence processing unit receives the plurality of task instructions through the predetermined protocol, and controls a plurality of circuits of a memory device according to the plurality of task instructions with at least one finite state machine of the sequence processing unit.
    Type: Application
    Filed: June 14, 2019
    Publication date: November 5, 2020
    Inventors: Huang Peng Zhang, XIANG FU, Qi Wang, Zhi Chao Du, Hua Min Cao, Xin Yun Huang, Wen Wen Dong, Shu Bing Xu
  • Publication number: 20200303456
    Abstract: The present disclosure relates to magnetic memory device. The magnetic memory device includes a bottom electrode, a selector layer disposed over the bottom electrode, and a MTJ stack disposed over the selector layer and comprising a reference layer and a free layer disposed over the reference layer and separated from the reference layer by a tunneling barrier layer. The magnetic memory device further includes a modulating layer disposed over the MTJ stack and a top electrode disposed over the switching threshold modulating layer. The modulating layer is configured to reinforce stability of the free layer by magnetically coupled to the free layer.
    Type: Application
    Filed: June 9, 2020
    Publication date: September 24, 2020
    Inventors: Katherine H. Chiang, Chung-Te Lin, Min Cao, Han-Ting Tsai, Pin-Cheng Hsu, Yen-Chung Ho
  • Patent number: 10755132
    Abstract: A method for extracting a surface deformation feature of an object based on linear scanning three-dimensional point cloud is disclosed comprising: performing data acquisition by using a three-dimensional measurement sensor based on line structured light, and obtaining a three-dimensional point cloud data of a surface of the object after data pre-processing; eliminating influences of abnormal data and textures on extraction of sectional main profiles, to accurately obtain the sectional main profiles of the object; obtaining a binary image based on deformation feature points extracted from sections, in conjunction with a deformation feature knowledge base, and preliminarily positioning a deformation region based on sub-block images to obtain a set of target morphology sub-blocks; then performing a morphological operation on deformation feature points in the set of target morphology sub-blocks, and generating a deformation region of confidence ROC, and then performing a region growth to extract a target using ge
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: August 25, 2020
    Assignee: WUHAN WUDA ZOYON SCIENCE AND TECHNOLOGY CO., LTD
    Inventors: Qingquan Li, Min Cao, Dejin Zhang, Hong Lin, Ying Chen
  • Patent number: 10731002
    Abstract: A semiaromatic copolyamide resin and a polyamide molding composition consisting of the same are provided, consisting of following repeat units: (A) 26-80 mol % of units derived from para-amino benzoic acid; (B) 4-70 mol % of units derived from 11-aminoundecanoic acid or undecanolactam, and 0-70 mol % of units derived from another amino acids having 6 to 36 carbon atoms or units consisting of a lactam having 6-36 carbon atoms; (C) 0-37 mol % of units derived from a diamine unit having 4 to 36 carbon atoms; and (D) 0-37 mol % of units derived from a diacid unit having 6 to 36 carbon atoms; wherein, (A)+(B)+(C)+(D)=100 mol %; and molar contents of the units derived from para-amino benzoic acid and those derived from 11-aminoundecanoic acid or undecanolactam are not equal to 50 mol % simultaneously.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: August 4, 2020
    Assignees: KINGFA SCI. & TECH. CO., LTD., ZHUHAI VANTEQUE SPECIALTY ENGINEERING PLASTICS CO., LTD., SHANGHAI KINGFA SCI. & TECH. DVPT. CO., LTD.
    Inventors: Chuanhui Zhang, Min Cao, Sujun Jiang, Zhenguo Shi, Xueke Sun, Liming Fan, Mingqin Chen, Mujun Huang, Xianbo Huang
  • Patent number: 10720442
    Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a plurality vertical memory strings disposed through an alternating conductor/dielectric stack. Each of the memory strings includes a composite dielectric layers and a TFET semiconductor layer. The TFET semiconductor layer includes an n-type semiconductor layer and a p-type semiconductor layer.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: July 21, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Xin Yun Huang, Qi Wang, Xiang Fu, Zhiliang Xia, Huang Peng Zhang, Hua Min Cao
  • Patent number: 10700125
    Abstract: The present disclosure relates to magnetic memory device. The magnetic memory device includes a bottom electrode, a selector layer disposed over the bottom electrode, and a MTJ stack disposed over the selector layer and comprising a reference layer and a free layer disposed over the reference layer and separated from the reference layer by a tunneling barrier layer. The magnetic memory device further includes a modulating layer disposed over the MTJ stack and a top electrode disposed over the switching threshold modulating layer. The selector layer is configured to switch current on and off based on applied bias.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: June 30, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Katherine H. Chiang, Chung-Te Lin, Min Cao, Han-Ting Tsai, Pin-Cheng Hsu, Yen-Chung Ho
  • Publication number: 20200152464
    Abstract: The present disclosure provides a method in accordance with some embodiments. The method includes forming a mandrel over a substrate, the mandrel having a first sidewall and a second sidewall opposing the first sidewall; forming a first fin on the first sidewall and a second fin on the second sidewall; depositing a dielectric material covering the first fin, the second fin, and the mandrel; partially removing the dielectric material, thereby exposing the second fin; etching the second fin without etching the first fin and the mandrel; removing the dielectric material; and removing the mandrel.
    Type: Application
    Filed: December 23, 2019
    Publication date: May 14, 2020
    Inventors: Chin-Yuan Tseng, Wei-Liang Lin, Li-Te Lin, Ru-Gun Liu, Min Cao
  • Publication number: 20200152666
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first fin active region of a first semiconductor material disposed within the first region, oriented in a first direction, wherein the first fin active region has a <100> crystalline direction along the first direction; and a second fin active region of a second semiconductor material disposed within the second region and oriented in the first direction, wherein the second fin active region has a <110> crystalline direction along the first direction.
    Type: Application
    Filed: January 13, 2020
    Publication date: May 14, 2020
    Inventors: Tzer-Min Shen, Zhiqiang Wu, Chung-Cheng Wu, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang, Min Cao
  • Publication number: 20200127046
    Abstract: Various embodiments of the present application are directed towards a bipolar selector having independently tunable threshold voltages, as well as a memory cell comprising the bipolar selector and a memory array comprising the memory cell. In some embodiments, the bipolar selector comprises a first unipolar selector and a second unipolar selector. The first and second unipolar selectors are electrically coupled in parallel with opposite orientations and may, for example, be diodes or some other suitable unipolar selectors. By placing the first and second unipolar selectors in parallel with opposite orientations, the first unipolar selector independently defines a first threshold voltage of the bipolar selector and the second unipolar selector independently defines a second threshold voltage of the bipolar selector. As a result, the first and second threshold voltages can be independently tuned by adjusting parameters of the first and second unipolar selectors.
    Type: Application
    Filed: May 14, 2019
    Publication date: April 23, 2020
    Inventors: Sheng-Chih Lai, Chung-Te Lin, Min Cao, Randy Osborne
  • Publication number: 20200126986
    Abstract: An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.
    Type: Application
    Filed: December 20, 2019
    Publication date: April 23, 2020
    Inventors: Ali KESHAVARZI, Ta-Pen GUO, Shu-Hui SUNG, Hsiang-Jen TSENG, Shyue-Shyh LIN, Lee-Chung LU, Chung-Cheng WU, Li-Chun TIEN, Jung-Chan YANG, Ting-Yu CHEN, Min CAO, Yung-Chin HOU
  • Publication number: 20200105830
    Abstract: The present disclosure relates to magnetic memory device. The magnetic memory device includes a bottom electrode, a selector layer disposed over the bottom electrode, and a MTJ stack disposed over the selector layer and comprising a reference layer and a free layer disposed over the reference layer and separated from the reference layer by a tunneling barrier layer. The magnetic memory device further includes a modulating layer disposed over the MTJ stack and a top electrode disposed over the switching threshold modulating layer. The selector layer is configured to switch current on and off based on applied bias.
    Type: Application
    Filed: May 20, 2019
    Publication date: April 2, 2020
    Inventors: Katherine H. Chiang, Chung-Te Lin, Min Cao, Han-Ting Tsai, Pin-Cheng Hsu, Yen-Chung Ho
  • Publication number: 20200105898
    Abstract: A first fin structure is disposed over a substrate. The first fin structure contains a semiconductor material. A gate dielectric layer is disposed over upper and side surfaces of the first fin structure. A gate electrode layer is formed over the gate dielectric layer. A second fin structure is disposed over the substrate. The second fin structure is physically separated from the first fin structure and contains a ferroelectric material. The second fin structure is electrically coupled to the gate electrode layer.
    Type: Application
    Filed: September 16, 2019
    Publication date: April 2, 2020
    Inventors: Chi-Hsing Hsu, Sai-Hooi Yeong, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang, Min Cao
  • Publication number: 20200075074
    Abstract: In some embodiments, the present disclosure relates to an integrated circuit. The integrated circuit has an operative magnetic tunnel junction (MTJ) device configured to store a data state. The operative MTJ device is coupled to a bit-line. A regulating access apparatus is coupled between the operative MTJ device and a first word-line. The regulating access apparatus has one or more regulating MTJ devices that are configured to control a current provided to the operative MTJ device.
    Type: Application
    Filed: September 5, 2018
    Publication date: March 5, 2020
    Inventors: Katherine Chiang, Chung Te Lin, Min Cao, Yuh-Jier Mii, Sheng-Chih Lai
  • Patent number: 10571256
    Abstract: A three-dimensional measurement sensor based on line structured light, comprising a sensing head and a controller. The sensing head is used for collecting section data and attitude information of its own, and matching the section data with the self attitude information. The sensing head comprises a three-dimensional camera, an attitude sensor, a laser and a control sub-board, wherein the three-dimensional camera is installed at a certain angle relative to the laser, and acquires elevation and grey information about an object surface corresponding to laser rays using a triangulation principle. The attitude sensor, the three-dimensional camera and the laser are installed on the same rigid plane, and the attitude sensor reflects measurement attitude of the three-dimensional camera and the laser in real time. The controller is used for measuring and controlling the sensing head, performing data processing transmission and supporting external control.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: February 25, 2020
    Assignee: WUHAN WUDA ZOYON SCIENCE AND TECHNOLOGY CO., LTD
    Inventors: Qingquan Li, Dejin Zhang, Min Cao, Xinlin Wang, Hong Lin