Patents by Inventor Min Cao

Min Cao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200105898
    Abstract: A first fin structure is disposed over a substrate. The first fin structure contains a semiconductor material. A gate dielectric layer is disposed over upper and side surfaces of the first fin structure. A gate electrode layer is formed over the gate dielectric layer. A second fin structure is disposed over the substrate. The second fin structure is physically separated from the first fin structure and contains a ferroelectric material. The second fin structure is electrically coupled to the gate electrode layer.
    Type: Application
    Filed: September 16, 2019
    Publication date: April 2, 2020
    Inventors: Chi-Hsing Hsu, Sai-Hooi Yeong, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang, Min Cao
  • Publication number: 20200105830
    Abstract: The present disclosure relates to magnetic memory device. The magnetic memory device includes a bottom electrode, a selector layer disposed over the bottom electrode, and a MTJ stack disposed over the selector layer and comprising a reference layer and a free layer disposed over the reference layer and separated from the reference layer by a tunneling barrier layer. The magnetic memory device further includes a modulating layer disposed over the MTJ stack and a top electrode disposed over the switching threshold modulating layer. The selector layer is configured to switch current on and off based on applied bias.
    Type: Application
    Filed: May 20, 2019
    Publication date: April 2, 2020
    Inventors: Katherine H. Chiang, Chung-Te Lin, Min Cao, Han-Ting Tsai, Pin-Cheng Hsu, Yen-Chung Ho
  • Publication number: 20200075074
    Abstract: In some embodiments, the present disclosure relates to an integrated circuit. The integrated circuit has an operative magnetic tunnel junction (MTJ) device configured to store a data state. The operative MTJ device is coupled to a bit-line. A regulating access apparatus is coupled between the operative MTJ device and a first word-line. The regulating access apparatus has one or more regulating MTJ devices that are configured to control a current provided to the operative MTJ device.
    Type: Application
    Filed: September 5, 2018
    Publication date: March 5, 2020
    Inventors: Katherine Chiang, Chung Te Lin, Min Cao, Yuh-Jier Mii, Sheng-Chih Lai
  • Patent number: 10571256
    Abstract: A three-dimensional measurement sensor based on line structured light, comprising a sensing head and a controller. The sensing head is used for collecting section data and attitude information of its own, and matching the section data with the self attitude information. The sensing head comprises a three-dimensional camera, an attitude sensor, a laser and a control sub-board, wherein the three-dimensional camera is installed at a certain angle relative to the laser, and acquires elevation and grey information about an object surface corresponding to laser rays using a triangulation principle. The attitude sensor, the three-dimensional camera and the laser are installed on the same rigid plane, and the attitude sensor reflects measurement attitude of the three-dimensional camera and the laser in real time. The controller is used for measuring and controlling the sensing head, performing data processing transmission and supporting external control.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: February 25, 2020
    Assignee: WUHAN WUDA ZOYON SCIENCE AND TECHNOLOGY CO., LTD
    Inventors: Qingquan Li, Dejin Zhang, Min Cao, Xinlin Wang, Hong Lin
  • Patent number: 10535655
    Abstract: An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ali Keshavarzi, Ta-Pen Guo, Shu-Hui Sung, Hsiang-Jen Tseng, Shyue-Shyh Lin, Lee-Chung Lu, Chung-Cheng Wu, Li-Chun Tien, Jung-Chan Yang, Ting-Yu Chen, Min Cao, Yung-Chin Hou
  • Patent number: 10535680
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first fin active region of a first semiconductor material disposed within the first region, oriented in a first direction, wherein the first fin active region has a <100> crystalline direction along the first direction; and a second fin active region of a second semiconductor material disposed within the second region and oriented in the first direction, wherein the second fin active region has a <110> crystalline direction along the first direction.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: January 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tzer-Min Shen, Zhiqiang Wu, Chung-Cheng Wu, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang, Min Cao
  • Patent number: 10535520
    Abstract: The present disclosure provides a method in accordance with some embodiments. The method includes forming a material layer that includes an array of fin features, wherein at least one fin feature has a first material on a first sidewall and a second material on a second sidewall that is opposite to the first sidewall, wherein the first material is different from the second material. The method further includes exposing the second sidewall of the at least one fin feature and removing the at least one fin feature.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: January 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chin-Yuan Tseng, Wei-Liang Lin, Li-Te Lin, Ru-Gun Liu, Min Cao
  • Publication number: 20190371383
    Abstract: In some embodiments, the present disclosure relates to an integrated circuit. The integrated circuit includes a first memory device and a second memory device arranged over a substrate. The first memory device is coupled to a first bit-line. The second memory device is coupled to a second bit-line. A shared control element is arranged within the substrate and is configured to provide access to the first memory device and to separately provide access to the second memory device. The shared control element includes one or more control devices sharing one or more components.
    Type: Application
    Filed: June 1, 2018
    Publication date: December 5, 2019
    Inventors: Katherine Chiang, Chung-Te Lin, Min Cao, Randy Osborne
  • Patent number: 10489903
    Abstract: The present invention discloses a stepwise refinement detection method for pavement cracks, processing pavement images comprising the following primary steps: extracting and processing marking lines, extracting ROA, adaptive threshold segmentation based on ROA, extracting ROC and region growth based on ROC direction feature weighting.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: November 26, 2019
    Assignee: WUHAN WUDA ZOYON SCIENCE AND TECHNOLOGY CO., LTD.
    Inventors: Qingquan Li, Dejin Zhang, Min Cao, Hong Lin
  • Publication number: 20190234728
    Abstract: A three-dimensional measurement sensor based on line structured light, comprising a sensing head and a controller. The sensing head is used for collecting section data and attitude information of its own, and matching the section data with the self attitude information. The sensing head comprises a three-dimensional camera, an attitude sensor, a laser and a control sub-board, wherein the three-dimensional camera is installed at a certain angle relative to the laser, and acquires elevation and grey information about an object surface corresponding to laser rays using a triangulation principle. The attitude sensor, the three-dimensional camera and the laser are installed on the same rigid plane, and the attitude sensor reflects measurement attitude of the three-dimensional camera and the laser in real time. The controller is used for measuring and controlling the sensing head, performing data processing transmission and supporting external control.
    Type: Application
    Filed: August 26, 2016
    Publication date: August 1, 2019
    Applicant: WUHAN WUDA ZOYON SCIENCE AND TECHNOLOGY CO., LTD
    Inventors: Qingquan LI, Dejin ZHANG, Min CAO, Xinlin WANG, Hong LIN
  • Patent number: 10335741
    Abstract: A method for preparing the network-pore polyvinylidene fluoride membrane based on polyvinyl alcohol (PVA) gel includes the steps of (1) mix and stir PVA, masking agent and solvent, heat and dissolve the mixture evenly under 105 degree Celsius to obtain a PVA solution; (2) in the PVA solution, add PVDF and pore-forming agent, where the rest shall be added with the solvent until the total mass fraction sum is 1, stir, heat and dissolve the solution evenly to obtain the homogeneous casting solution; (3) the casting solution is filtered, deaerated, phase-separated and solidified as membrane A; (4) removes the PVA gel from membrane A to obtain membrane B; (5) membrane B is washed with water to remove the residual solvent to obtain the PVDF membrane with network-pore structure. The resulting PVDF membrane is an asymmetric membrane with an ultra-thin cortex and an interpenetrating network-pore sub-cortex structure.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: July 2, 2019
    Assignee: JIANGSU KAIMI MEMBRANE TECHNOLOGY CO., LTD
    Inventors: Na Peng, Huailin Wang, Jinming Yun, Min Cao, Hang Yin, Liangjing Shi
  • Publication number: 20190197340
    Abstract: A method for extracting a surface deformation feature of an object based on linear scanning three-dimensional point cloud is disclosed comprising: performing data acquisition by using a three-dimensional measurement sensor based on line structured light, and obtaining a three-dimensional point cloud data of a surface of the object after data pre-processing; eliminating influences of abnormal data and textures on extraction of sectional main profiles, to accurately obtain the sectional main profiles of the object; obtaining a binary image based on deformation feature points extracted from sections, in conjunction with a deformation feature knowledge base, and preliminarily positioning a deformation region based on sub-block images to obtain a set of target morphology sub-blocks; then performing a morphological operation on deformation feature points in the set of target morphology sub-blocks, and generating a deformation region of confidence ROC, and then performing a region growth to extract a target using ge
    Type: Application
    Filed: January 25, 2016
    Publication date: June 27, 2019
    Applicant: WUHAN WUDA ZOYON SCIENCE AND TECHNOLOGY CO., LTD.
    Inventors: Qingquan LI, Min CAO, Dejin ZHANG, Hong LIN, Ying CHEN
  • Publication number: 20190081068
    Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a plurality vertical memory strings disposed through an alternating conductor/dielectric stack. Each of the memory strings includes a composite dielectric layers and a TFET semiconductor layer. The TFET semiconductor layer includes an n-type semiconductor layer and a p-type semiconductor layer.
    Type: Application
    Filed: July 26, 2018
    Publication date: March 14, 2019
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventors: Xin Yun HUANG, Qi Wang, Xiang Fu, Zhiliang Xia, Huang Peng Zhang, Hua Min Cao
  • Publication number: 20190006391
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first fin active region of a first semiconductor material disposed within the first region, oriented in a first direction, wherein the first fin active region has a <100> crystalline direction along the first direction; and a second fin active region of a second semiconductor material disposed within the second region and oriented in the first direction, wherein the second fin active region has a <110> crystalline direction along the first direction.
    Type: Application
    Filed: November 1, 2017
    Publication date: January 3, 2019
    Inventors: Tzer-Min Shen, Zhiqiang Wu, Chung-Cheng Wu, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang, Min Cao
  • Publication number: 20190002639
    Abstract: The present invention discloses a semiaromatic copolyamide resin and a polyamide molding composition consisting of the same, consisting of following repeat units: (A) 26-80 mol % of units derived from para-amino benzoic acid; (B) 4-70 mol % of units derived from 11-aminoundecanoic acid or undecanolactam, and 0-70 mol % of units derived from another amino acids having 6 to 36 carbon atoms or units consisting of a lactam having 6-36 carbon atoms; (C) 0-37 mol % of units derived from a diamine unit having 4 to 36 carbon atoms; and (D) 0-37 mol % of units derived from a diacid unit having 6 to 36 carbon atoms; wherein, (A)+(B)+(C)+(D)=100 mol %; and molar contents of the units derived from para-amino benzoic acid and those derived from 11-aminoundecanoic acid or undecanolactam are not equal to 50 mol % simultaneously.
    Type: Application
    Filed: March 29, 2017
    Publication date: January 3, 2019
    Applicants: KINGFA SCI. & TECH. CO., LTD., ZHUHAI VANTEQUE SPECIALTY ENGINEERING PLASTICS CO., LTD., SHANGHAI KINGFA SCI. & TECH. DVPT. CO., LTD.
    Inventors: Chuanhui ZHANG, Min CAO, Sujun JIANG, Zhenguo SHI, Xueke SUN, Liming FAN, Mingqin CHEN, Mujun HUANG, Xianbo HUANG
  • Publication number: 20190002638
    Abstract: The present invention discloses a semiaromatic polyamide resin, a preparation method thereof, and a polyamide molding composition consisting of the same, which consists of following components: (A) 20 to 95 wt % of a PA10T homopolymer derived from 1,10-decanediamine and terephthalic acid; and (B) 5 to 80 wt % of a PA6T homopolymer derived from 1,6-hexanediamine and terephthalic acid. Particularly, (A)+(B)=100 wt %. In the present invention, by adding a certain amount of the PA10T homopolymer into the PA6T homopolymer, a melting point of the PA6T homopolymer can be significantly decreased to be below a decomposition temperature thereof, and thereby a processability of the PA6T homopolymer is improved. The prepared semiaromatic polyamide resin has a decreased melting point, and may be processed normally. The polyamide molding composition consisting of the semiaromatic polyamide resin has a good processability, and has excellent surface properties.
    Type: Application
    Filed: June 9, 2017
    Publication date: January 3, 2019
    Applicants: KINGFA SCI. & TECH. CO., LTD., ZHUHAI VANTEQUE SPECIALTY ENGINEERING PLASTICS CO., LTD.
    Inventors: Chuanhui ZHANG, Min CAO, Sujun JIANG, Xianbo HUANG, Jiehong MAI, Jieming LONG, Zhenguo SHI, Kun YAN, Liming FAN
  • Publication number: 20180315602
    Abstract: The present disclosure provides a method in accordance with some embodiments. The method includes forming a material layer that includes an array of fin features, wherein at least one fin feature has a first material on a first sidewall and a second material on a second sidewall that is opposite to the first sidewall, wherein the first material is different from the second material. The method further includes exposing the second sidewall of the at least one fin feature and removing the at least one fin feature.
    Type: Application
    Filed: August 23, 2017
    Publication date: November 1, 2018
    Inventors: Chin-Yuan Tseng, Wei-Liang Lin, Li-Te Lin, Ru-Gun Liu, Min Cao
  • Patent number: 10091730
    Abstract: The present disclosure discloses a method and network device for adaptive management of wireless clients based on clients' radio behaviors and capabilities. Specifically, a disclosed network device can dynamically select a location tracking mechanism based on a probing characteristic of a client device. The disclosed network device can also dynamically selects a communication mechanism based on a power saving characteristics of a client device. Moreover, the disclosed network device can determine whether to select a new access point for a client device based on roaming characteristics of the client device. The adaptive management of client devices can be performed on a group of client devices with similar radio behaviors and/or capabilities on a per-radio rather than per-BSSID (basic service set identifier) basis.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: October 2, 2018
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Min Cao, Partha Narasimhan
  • Patent number: 10049175
    Abstract: Some aspects enable users to interactively define a region in an electronic design, identify or generate a track pattern, and assign the track pattern to the region for subsequent physical implementation for the region. Another aspect interactively represents various results on a display apparatus using one or more distinguishing representation schemes. Another aspect is directed at interactive editing a component of an electronic design having track patterns by iteratively modifying a set of track patterns to reach a reduced set of track patterns and by automatically snapping the component to active track(s) in the reduced set for the physical implementation.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: August 14, 2018
    Assignee: Cadence Design Systems, Inc.
    Inventors: Jeffrey S. Salowe, Min Cao, Roland Ruehl, Jeffrey Markham
  • Publication number: 20180154314
    Abstract: A method for preparing the network-pore polyvinylidene fluoride membrane based on polyvinyl alcohol (PVA) gel includes the steps of (1) mix and stir PVA, masking agent and solvent, heat and dissolve the mixture evenly under 105 degree Celsius to obtain a PVA solution; (2) in the PVA solution, add PVDF and pore-forming agent, where the rest shall be added with the solvent until the total mass fraction sum is 1, stir, heat and dissolve the solution evenly to obtain the homogeneous casting solution; (3) the casting solution is filtered, deaerated, phase-separated and solidified as membrane A; (4) removes the PVA gel from membrane A to obtain membrane B; (5) membrane B is washed with water to remove the residual solvent to obtain the PVDF membrane with network-pore structure. The resulting PVDF membrane is an asymmetric membrane with an ultra-thin cortex and an interpenetrating network-pore sub-cortex structure.
    Type: Application
    Filed: August 2, 2016
    Publication date: June 7, 2018
    Inventors: PENG Na, Huailin WANG, Jinming YUN, Min CAO, Hang YIN, Liangjing SHI