Abstract: The present disclosure provides a method of forming a semiconductor device including an nFET structure and a pFET structure where each of the nFET and pFET structures include a semiconductor substrate and a gate trench. The method includes depositing an interfacial layer in each gate trench, depositing a first ferroelectric layer over the interfacial layer, removing the first ferroelectric layer from the nFET structure, depositing a metal oxide layer in each gate trench, depositing a second ferroelectric layer over the metal oxide layer, removing the second ferroelectric layer from the pFET structure, and depositing a gate electrode in each gate trench.

Abstract: An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.

Abstract: A system for generation and distribution of data handling requirements associated with sensitive data among a plurality of computing networks is described. Specifically, data generated at a first computing network may be tagged with associated data handling requirements. A reference library entry may be generated to include an indicator of the data and the associated data handling requirements. The reference library entry may be distributed to the plurality of computing networks, wherein each of the plurality of computing networks may add the reference library entry to corresponding reference libraries. Updates to the reference library entry, made at any one of the plurality of computing networks, may be propagated to other computing networks such that an updated listing of data handling requirements is accessible to users associated with the plurality of computing networks.

Abstract: Aspects of the disclosure relate to multi-dimensional data tagging and reuse. A computing platform may receive first response data associated with responses to a first set of queries. Subsequently, the computing platform may apply data tags to the first response data, which may include tagging the first response data based on multiple dimensions. Then, the computing platform may prompt a user of a computing device from which the data originated to validate the data tags applied to the first response data. Next, the computing platform may analyze a second set of queries which may be associated with the same content type. Thereafter, the computing platform may generate second response data associated with responses to the second set of queries based on the data tags applied to the first response data and send the second response data in response to the second set of queries.

Abstract: A remote reconfiguration system for an Internet of Things (IoT) intelligent sensing terminal includes: a controlled terminal with a field programmable gate array (FPGA); and a remote control unit connected to the controlled terminal and a control device; where the remote control unit is configured to receive control information sent by the control device, process the control information and send the processed control information to the FPGA, such that the FPGA performs remote local autonomous reconfiguration based on the preprocessed control information. The system resolves problems that a traditional IoT terminal cannot realize remote control and cannot follow functional requirements to perform local autonomous reconfiguration, and has better versatility and expandability.

Abstract: Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a second contact feature over the first contact feature, a barrier layer between the second dielectric layer and the second contact feature, and a liner between the barrier layer and the second contact feature. An interface between the first contact feature and the second contact feature includes the liner but is free of the barrier layer.

Abstract: The present disclosure provides a method of forming a semiconductor device including an nFET structure and a pFET structure where each of the nFET and pFET structures include a semiconductor substrate and a gate trench. The method includes depositing an interfacial layer in each gate trench; depositing a first metal oxide layer over the interfacial layer; removing the first metal oxide layer from the pFET structure; depositing a ferroelectric layer in each gate trench; depositing a second metal oxide layer over the ferroelectric layer; removing the second metal oxide layer from the nFET structure; and depositing a gate electrode in each gate trench.

Abstract: An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.

Abstract: Semiconductor devices including backside capacitors and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure, the front-side interconnect structure including a front-side conductive line; a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a backside conductive line, the backside conductive line having a line width greater than a line width of the front-side conductive line; and a first capacitor structure coupled to the backside interconnect structure.

Abstract: Sequence-block copolymers have well-controlled and precise monomer sequence. A highly ordered fluoro-containing block copolymer material can be prepared based on the sequence-block copolymer, which shows excellent patterning capability.

Abstract: A micro-cavity liquid-phase shearing device for preparing quasi-two-dimensional materials includes a movable plate system, a fixed plate system, a feed liquid external circulation system, a driven gear system and a charging barrel. The movable plate system includes a movable plate unit and a driving gear. The fixed plate system includes a fixed plate unit and a support. A tank of the movable plate unit has a primary shear cavity, an annular micro-gap between a movable plate of the movable plate unit and a fixed plate of the fixed plate unit is defined as a secondary shear micro-cavity. The feed liquid, which flows outside the feed pipe through the liquid discharge port thereof, is primarily sheared in the primary shear cavity by the movable plate system, and then is secondarily sheared in the secondary shear micro-cavity by the movable plate and the fixed plate, and then returns to the charging barrel.

Abstract: Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a second contact feature over the first contact feature, a barrier layer between the second dielectric layer and the second contact feature, and a liner between the barrier layer and the second contact feature. An interface between the first contact feature and the second contact feature includes the liner but is free of the barrier layer.

Abstract: Various embodiments of the present application are directed towards a bipolar selector having independently tunable threshold voltages, as well as a memory cell comprising the bipolar selector and a memory array comprising the memory cell. In some embodiments, the bipolar selector comprises a first unipolar selector and a second unipolar selector. The first and second unipolar selectors are electrically coupled in parallel with opposite orientations and may, for example, be diodes or some other suitable unipolar selectors. By placing the first and second unipolar selectors in parallel with opposite orientations, the first unipolar selector independently defines a first threshold voltage of the bipolar selector and the second unipolar selector independently defines a second threshold voltage of the bipolar selector. As a result, the first and second threshold voltages can be independently tuned by adjusting parameters of the first and second unipolar selectors.

Abstract: The present disclosure provides a method of forming a semiconductor structure. The method includes providing a semiconductor substrate and forming a patterned metal structure on the semiconductor substrate, wherein the patterned metal structure includes a first metal layer and a second metal layer deposited in a single deposition step. The method further includes etching a portion of the second metal layer thereby forming a metal plug in the second metal layer, the first metal layer of the patterned metal structure having a first metal feature underlying and contacting the metal plug.

Abstract: An apparatus includes a memory and a processor. The memory stores descriptions of known vulnerabilities and information generated by a monitoring subsystem. Each description of a known vulnerability identifies software components that are associated with the known vulnerability. The monitoring subsystem monitors software programs that are installed within a computer system. The information includes descriptions of issues that are associated with the software programs. The processor generates a set of mappings, based on a comparison between the text describing the known software vulnerabilities and the text describing the issues. Each mapping associates a software program that is associated with an issue with a known software vulnerability. The processor also uses a machine learning algorithm to predict that a given software program is associated with a particular software vulnerability.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a first fin projecting vertically from a semiconductor substrate. A second fin projects vertically from the semiconductor substrate, where the second fin is spaced from the first fin, and where the first fin has a first uppermost surface that is disposed over a second uppermost surface of the second fin. A nanostructure stack is disposed over the second fin and vertically spaced from the second fin, where the nanostructure stack comprises a plurality of vertically stacked semiconductor nanostructures. A pair of first source/drain regions is disposed on the first fin, where the first source/drain regions are disposed on opposite sides of an upper portion of the first fin. A pair of second source/drain regions is disposed on the second fin, where the second source/drain regions are disposed on opposite sides of the nanostructure stack.

Abstract: The invention discloses an in situ polymerized flame retardant, derived from the following monomers: a diacid monomer A: where A1 is terephthalic acid, A2 is a phosphorus aromatic ring-containing reactive flame-retardant diacid monomer, A1+A2=100 mol %, A1=50 to 90 mol %, A2=10 to 50 mol %; and a diamine monomer B: one or more of diamine monomers containing 4 to 36 carbon atoms. In the present invention, a novel flame retardant is obtained by in situ polymerization of the phosphorus aromatic ring-containing reactive flame-retardant diacid monomers in semi-aromatic polyamide oligomers, which has advantages of no precipitation in the semi-aromatic polyamide and no influence on other properties of the semi-aromatic polyamide and has an excellent flame-retardant property.

Abstract: A resin including a highly sequenced copolymer is presented, and the preparation and application of its resist composition is presented. The resist has excellent performance and can promote the development of integrated circuits.

Abstract: Various embodiments of the present application are directed towards a bipolar selector having independently tunable threshold voltages, as well as a memory cell comprising the bipolar selector and a memory array comprising the memory cell. In some embodiments, the bipolar selector comprises a first unipolar selector and a second unipolar selector. The first and second unipolar selectors are electrically coupled in parallel with opposite orientations and may, for example, be diodes or some other suitable unipolar selectors. By placing the first and second unipolar selectors in parallel with opposite orientations, the first unipolar selector independently defines a first threshold voltage of the bipolar selector and the second unipolar selector independently defines a second threshold voltage of the bipolar selector. As a result, the first and second threshold voltages can be independently tuned by adjusting parameters of the first and second unipolar selectors.

Abstract: The invention discloses a flame-retardant semi-aromatic polyamide derived from the following monomers: a diacid monomer A: where A1 is terephthalic acid or terephthalic acid and other diacid, terephthalic acid accounts for 50 to 100 mol % of A1, and A2 is [(6-oxido-6H-dibenzo-(c,e)(1,2)-oxaphosphorin-6-ketone)-methyl]-butanedioic acid, A1+A2=100 mol %, A1=90 to 99 mol %, A2=1 to 10 mol %; and diamine monomer B: one or more of diamine monomers containing 4 to 36 carbon atoms. In the present invention, by an in situ polymerization, a specific flame-retardant monomer [(6-oxido-6H-dibenzo-(c,e)(1,2)-oxaphosphorin-6-ketone)-methyl]-butanedioic acid is copolymerized in a semi-aromatic polyamide chain segment, excellent mechanical properties and low water absorption can be obtained.