Abstract: A flavoring sheet with improved physical properties, a smoking article including the same, and methods of producing the flavoring sheet and the smoking article are provided. The flavoring sheet according to some embodiments of the present disclosure may include a hydrocolloid material configured to form a sheet, a flavoring, and a plasticizer. The plasticizer can improve physical properties of the flavoring sheet and thus enhance workability of a process of cutting the flavoring sheet.

Abstract: The present disclosure relates to the preparation of citrullinated vimentin antigen-specific immune tolerogenic dendritic cells and a composition for preventing or treating heart failure after myocardial infarction comprising the same. According to the present disclosure, it is confirmed that immune tolerogenic dendritic cells differentiated by treating immature dendritic cells with citrullinated vimentin regulate the expression of immune-related factors and have an excellent therapeutic effect on heart failure caused by myocardial infarction.

Abstract: A semiconductor circuit includes a first pad, a second pad, swapping circuit, and an internal circuit. The internal circuit receives a first external signal and a second external signal, and generates a first internal signal and a second internal signal. Based on master information and swapping information, the swapping circuit couples the internal circuit to one of first and second pads to provide a path through which the first internal signal is output and a path through which the first external signal is received, and couples the internal circuit to the other of the first and second pads to provide a path through which the second internal signal is output and a path through which the second external signal is received.

Abstract: The present disclosure discloses a preview vehicle height control system and a method of controlling the same. The system includes a monitoring device configured to detect the road surface condition of a driving path of a vehicle, an active suspension configured to adjust a vehicle height, a memory configured to store a plurality of data maps distinguished based on a type of bump, each data map having a vehicle dynamic characteristic as an input and a tuning factor as an output, and a controller configured to derive the tuning factor based on a data map, among the plurality of data maps of the memory, corresponding to the bump detected by the monitoring device, derive a target vehicle height in a form of a Gaussian distribution by substituting the tuning factor, and control the active suspension to follow the derived target vehicle height.

Abstract: A suspension includes a knuckle to which a wheel of a vehicle is fastened, a steering drive portion connected to the knuckle, a lower arm positioned at a lower end portion of the steering drive portion and including a first end portion connected to the knuckle and a second end portion connected to a vehicle body frame, a connecting link including a first end portion connected to an upper end portion of the steering drive portion, an upper arm connected to a second end portion of the connecting link, a damper connecting the upper arm and the vehicle body frame, and a push rod including a first end portion connected to the upper arm and a second end portion connected to the lower arm.

Abstract: A vehicle-height control system of an independent corner module, includes a suspension link connected to a wheel and configured to be rotated according to upward-downward displace of the wheel, a gear unit connected to a vehicle body and a rotational center portion of the suspension link and configured to receive a rotation force from the suspension link, a control torsion bar, a first end portion thereof being connected to the gear unit and the second end portion thereof being connected to a torsion variation unit, the torsion variation unit applying a drive force to adjust a height of the control torsion bar and to maintain the adjusted height, and a controller connected to the torsion variation unit and adjusting the height of the control torsion bar.

Abstract: A functional safety system of a robot according to an exemplary embodiment of the present disclosure can generate a safety zone which is a zone to sense whether an obstacle is present.

Abstract: A functional safety system of a robot according to an exemplary embodiment of the present disclosure can duplicate modules so as to satisfy a performance level d (pl-d) required for the functional satisfy of a robot.

Abstract: A functional safety system of a robot according to an exemplary embodiment of the present disclosure can duplicate modules so as to satisfy a performance level d (pl-d) required for the functional satisfy of a robot.

Abstract: An electrode including a current collector; and an electrode active material layer disposed on at least one surface of the current collector is disclosed. The electrode active material layer includes a lower layer region facing the current collector, and an upper layer region facing the lower layer region and extended to the surface of the electrode active material layer. The lower layer region includes a first active material and a first non-rubbery binder and is free from a rubbery binder. The upper layer region includes a second active material, a second non-rubbery binder, and a rubbery binder. The rubbery binder is a hydrogenated nitrile butadiene rubber (H-NBR). Each of the first non-rubbery binder and the second non-rubbery binder includes a polyvinylidene fluoride (PVDF)-based polymer, and the weight ratio of the second non-rubbery binder to the rubbery binder in the upper layer region is 1:0.03-1:0.07.

Abstract: A memory system includes: a first memory module including first volatile memories; a second memory module including second volatile memories, non-volatile memories and a module controller; a memory controller controlling the first and second memory modules through second and third control buses, respectively; and a switch array electrically coupling the second and third control buses, wherein the module controller controls the switch array to electrically couple the second and third control buses in a backup operation for backing up data of the first volatile memories to the non-volatile memories, wherein the first and second memory modules include one or more first memory stacks and one or more second memory stacks, respectively, wherein the first volatile memories are stacked in the first memory stacks, and wherein the second volatile memories, the non-volatile memories and the module controller are stacked in the second memory stacks.

Abstract: A semiconductor circuit includes a first pad, a second pad, swapping circuit, and an internal circuit. The internal circuit receives a first external signal and a second external signal, and generates a first internal signal and a second internal signal. Based on master information and swapping information, the swapping circuit couples the internal circuit to one of first and second pads to provide a path through which the first internal signal is output and a path through which the first external signal is received, and couples the internal circuit to the other of the first and second pads to provide a path through which the second internal signal is output and a path through which the second external signal is received.

Abstract: A memory system includes: a first memory module including first volatile memories; a second memory module including second volatile memories, non-volatile memories and a module controller; a memory controller controlling the first and second memory modules through second and third control buses, respectively; and a switch array electrically coupling the second and third control buses, wherein the module controller controls the switch array to electrically couple the second and third control buses in a backup operation for backing up data of the first volatile memories to the non-volatile memories, wherein the first and second memory modules include one or more first memory stacks and one or more second memory stacks, respectively, wherein the first volatile memories are stacked in the first memory stacks, and wherein the second volatile memories, the non-volatile memories and the module controller are stacked in the second memory stacks.

Abstract: A display device includes: an array substrate including a pixel array in a display area; an encapsulation substrate facing the array substrate; and a sealing member in a sealing area and between the array substrate and the encapsulation substrate. The array substrate includes: an organic insulation layer in a peripheral area between the display area and the sealing area; a power bus line in the peripheral area and including a first wiring layer and a second wiring layer that overlap the organic insulation layer; and a compensation pattern disposed under the sealing member, extending along an outer edge of the sealing member, and including a first compensation layer and a second compensation layer. The first compensation layer is connected to the first wiring layer, and the second compensation layer is on the first compensation layer and connected to the second wiring layer.

Abstract: A display device includes a voltage wiring pattern in a non-display area and connected to a display area, and between a pad area and the voltage wiring pattern, a metal wiring pattern in the non-display area and connecting the pad area to the voltage wiring pattern, and a sealing member between the pad area and the voltage wiring pattern, and coupling the display panel to an encapsulation substrate. The metal wiring pattern including a lead-in portion connected to the pad area, an overlapping portion overlapping the sealing member, and a connection portion connecting the overlapping portion to the voltage wiring pattern. The overlapping portion includes a first portion corresponding to the lead-in portion, a second portion corresponding to the connection portion, and a third portion extending from the second portion in a direction away from the first portion.

Abstract: A memory system includes: a first memory module including first volatile memories; a second memory module including second volatile memories, non-volatile memories and a module controller; a memory controller controlling the first and second memory modules through second and third control buses, respectively; and a switch array electrically coupling the second and third control buses, wherein the module controller controls the switch array to electrically couple the second and third control buses in a backup operation for backing up data of the first volatile memories to the non-volatile memories, wherein the first and second memory modules include one or more first memory stacks and one or more second memory stacks, respectively, wherein the first volatile memories are stacked in the first memory stacks, and wherein the second volatile memories, the non-volatile memories and the module controller are stacked in the second memory stacks.

Abstract: A signal receiving circuit includes a summing circuit, a clocked latch circuit and a feedback circuit. The summing circuit generates a summing signal based on an input signal and a feedback signal. The clocked latch circuit generates a sampling signal by sampling the summing signal in synchronization with a clock signal. The feedback circuit generates the feedback signal by selecting one among a plurality of coefficients based on the sampling signal.

Abstract: A memory system includes: a first memory module including first volatile memories; a second memory module including second volatile memories, non-volatile memories and a module controller; a memory controller controlling the first and second memory modules through second and third control buses, respectively; and a switch array electrically coupling the second and third control buses, wherein the module controller controls the switch array to electrically couple the second and third control buses in a backup operation for backing up data of the first volatile memories to the non-volatile memories, wherein the first and second memory modules include one or more first memory stacks and one or more second memory stacks, respectively, wherein the first volatile memories are stacked in the first memory stacks, and wherein the second volatile memories, the non-volatile memories and the module controller are stacked in the second memory stacks.

Abstract: A signal receiver circuit includes: a negative voltage applier suitable for applying a negative voltage to a common source node in response to a first clock is at a first logic level; a first sampling transistor coupled between the common source node and a first sampling node to sink a current from the first sampling node to the common source node in response to a first input signal; a second sampling transistor coupled between the common source node and a second sampling node to sink a current from the second sampling node to the common source node in response to a second input signal; an equalizer suitable for equalizing the first sampling node and the second sampling node in response to the first clock is at a second logic level; a precharger suitable for precharging a first output node and a second output node with a pull-up voltage in response to a second clock is at the first logic level, and electrically coupling the first output node and second output node to the second sampling node and the first sam

Abstract: A memory system includes: a memory module including: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; and a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (OS) and an application to access a data storage memory through the first and second memory devices.