Abstract: A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (OS) and an application to access a data storage memory through the first and second memory devices.

Abstract: A first data input circuit receives test data from a first pad to generate first input control data for generating cell input data stored in a memory cell array during a first operation period. A first data output circuit receives first output control data generated from cell output data outputted from the memory cell array to output the first output control data to an internal node coupled to a second pad during a second operation period.

Abstract: A semiconductor system may include a first semiconductor device including a first pad group. The semiconductor system may include a second semiconductor device including a second pad group which is configured for input and output of signals from and to a third semiconductor device. The second semiconductor device may include a selective transfer unit configured to electrically couple the third pad group to the first pad group or to an interface unit electrically coupled to the first pad group, in response to a test mode enable signal.

Abstract: A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs an external command and external addresses. The second semiconductor device generates an internal active command in response to the external command, generates active addresses in response to the external addresses, generates a refresh signal and refresh addresses in response to the internal active command, performs an internal operation in response to the internal active command and the active addresses, and performs a refresh operation in response to the refresh signal and the refresh addresses.

Abstract: A semiconductor device may include a buffer control signal generation circuit, an input control signal generation circuit and an internal data generation circuit. The buffer control signal generation circuit may be configured to generate a buffer control signal. The buffer control signal may be enabled in synchronization with a point of time that a predetermined section elapses from a point of time that a write command signal is generated. The input control signal generation circuit may be configured to receive a data strobe signal to generate an input control signal, in response to the buffer control signal. The internal data generation circuit may be configured to receive a data signal to generate internal data.

Abstract: A semiconductor memory device includes a plurality of memory cells coupled to multiple word lines a word line deactivation voltage generation block suitable for generating word line deactivation voltages having different voltage levels corresponding to temperature ranges, and a word line driving block suitable for driving a word line to be deactivated with the word line deactivation voltages selected from the word line deactivation voltages.

Abstract: A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may output an external strobe signal and external data. The second semiconductor device may extract error information from the external data in synchronization with the external strobe signal during a write operation and outputs the external data and the error information through input/output (I/O) lines during the write operation. The second semiconductor device may correct errors of internal data with the error information loaded on the I/O lines to output the corrected internal data as the external data during a read operation.

Abstract: A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs data, a data strobe signal, an external command, and a clock signal. The second semiconductor device aligns the data in synchronization with the data strobe signal to generate first and second alignment data and latches the first and second alignment data to generate first and second latch data in response to a latch signal which is generated by dividing the data strobe signal.

Abstract: A semiconductor memory device includes a plurality of memory cells coupled to multiple word lines a word line deactivation voltage generation block suitable for generating word line deactivation voltages having different voltage levels corresponding to temperature ranges, and a word line driving block suitable for driving a word line to be deactivated with the word line deactivation voltages selected from the word line deactivation voltages.

Abstract: A semiconductor device may include a buffer control signal generation circuit, an input control signal generation circuit and an internal data generation circuit. The buffer control signal generation circuit may be configured to generate a buffer control signal. The buffer control signal may be enabled in synchronization with a point of time that a predetermined section elapses from a point of time that a write command signal is generated. The input control signal generation circuit may be configured to receive a data strobe signal to generate an input control signal, in response to the buffer control signal. The internal data generation circuit may be configured to receive a data signal to generate internal data.

Abstract: A semiconductor device may include a buffer control signal generation circuit, an input control signal generation circuit and an internal data generation circuit. The buffer control signal generation circuit may be configured to generate a buffer control signal. The buffer control signal may be enabled in synchronization with a point of time that a predetermined section elapses from a point of time that a write command signal is generated. The input control signal generation circuit may be configured to receive a data strobe signal to generate an input control signal, in response to the buffer control signal. The internal data generation circuit may be configured to receive a data signal to generate internal data.

Abstract: A parallel test device and method are disclosed, which relates to a technology for performing a multi-bit parallel test by compressing data. The parallel test device includes: a pad unit through which data input/output (I/O) operations are achieved; a plurality of input buffers configured to activate write data received from the pad unit in response to a buffer enable signal, and output the write data to a global input/output (GIO) line; a plurality of output drivers configured to activate read data received from the global I/O (GIO) line in response to a strobe delay signal, and output the read data to the pad unit; and a test controller configured to activate the buffer enable signal and the strobe delay signal during a test mode in a manner that the read data received from the plurality of output drivers is applied to the plurality of input buffers such that the read data is operated as the write data.

Abstract: A semiconductor apparatus may include a first data processing block electrically coupled between a first input/output pad array and a first memory array. The semiconductor apparatus may include a second data processing block electrically coupled between a second input/output pad array and a second memory array. The first test verification data and second test verification data may be generated by causing data to be respectively outputted from the first memory array and the second memory array to pass through the first data processing block and the second data processing block, according to a read command and a plurality of control signals. The first test verification data and the second test verification data may be respectively written again in the first memory array and the second memory array. A result of comparing the first test verification data and the second test verification data may be outputted through the first input/output pad array.

Abstract: A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs data, a data strobe signal, an external command, and a clock signal. The second semiconductor device aligns the data in synchronization with the data strobe signal to generate first and second alignment data and latches the first and second alignment data to generate first and second latch data in response to a latch signal which is generated by dividing the data strobe signal.

Abstract: A method of manufacturing an organic light-emitting diode (OLED) display is disclosed. In one aspect, the method includes forming an OLED over a first substrate and forming a sealing member over the first substrate or a second substrate opposite to the first substrate, to at least partially surround the OLED, wherein a plurality of holes are defined in a first region of the sealing member. The method further includes aligning the first and second substrates with the sealing member interposed therebetween and irradiating a laser beam along a path of the sealing member.

Abstract: A parallel test device and method are disclosed, which relates to a technology for performing a multi-bit parallel test by compressing data. The parallel test device includes: a pad unit through which data input/output (I/O) operations are achieved; a plurality of input buffers configured to activate write data received from the pad unit in response to a buffer enable signal, and output the write data to a global input/output (GIO) line; a plurality of output drivers configured to activate read data received from the global I/O (GIO) line in response to a strobe delay signal, and output the read data to the pad unit; and a test controller configured to activate the buffer enable signal and the strobe delay signal during a test mode in a manner that the read data received from the plurality of output drivers is applied to the plurality of input buffers such that the read data is operated as the write data.

Abstract: This technique may include a semiconductor apparatus configured to perform data read/write operations in a test mode or a normal mode and a tester configured to simultaneously perform a data test and a leakage current test through a write operation using data read by a read operation in the normal mode after writing data into the semiconductor apparatus in the test mode.

Abstract: A microspeaker includes a frame, magnetic circuit, voice coil configured to generate vibration by mutual electromagnetic force with the magnetic circuit, vibration plate configured to vibrate together according to the vibration of the voice coil to generate a sound, and suspension configured to guide a vibration direction of the vibration plate and voice coil. The suspension has a central portion attached to the voice coil, an annular outer circumferential portion formed to be spaced apart from the central portion by a predetermined interval, and a connection portion connecting the central and outer circumferential portions and configured to perform a damping function. The central portion has an outer end having the same height as the connection and outer circumferential portions, an inner end positioned to be higher than the outer end, and a step portion connecting the outer end and inner end. The voice coil is attached to the inner end.

Abstract: A method of manufacturing an organic light-emitting diode (OLED) display is disclosed. In one aspect, the method includes forming an OLED over a first substrate and forming a sealing member over the first substrate or a second substrate opposite to the first substrate, to at least partially surround the OLED, wherein a plurality of holes are defined in a first region of the sealing member. The method further includes aligning the first and second substrates with the sealing member interposed therebetween and irradiating a laser beam along a path of the sealing member.

Abstract: A semiconductor system may include a first semiconductor device including a first pad group. The semiconductor system may include a second semiconductor device including a second pad group which is configured for input and output of signals from and to a third semiconductor device. The second semiconductor device may include a selective transfer unit configured to electrically couple the third pad group to the first pad group or to an interface unit electrically coupled to the first pad group, in response to a test mode enable signal.