Patents by Inventor Min Cheng

Min Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250014491
    Abstract: A driving module includes N driving circuits connected in series; the driving circuit includes an input terminal; N is a positive integer; input terminals of first a stages of driving circuits included in the driving module are electrically connected to an initial voltage line; a is a positive integer; an input terminal of an nth stage of driving circuit included in the driving module is electrically connected to an output terminal of an (n?m)th stage of driving circuit included in the driving module through an input cascade line; n and m are positive integers, and m is less than n; the driving module further includes at least one connection line, there is an overlapping portion between an orthographic projection of the connection line on the base substrate and an orthographic projection of the initial voltage line on the base substrate.
    Type: Application
    Filed: September 23, 2022
    Publication date: January 9, 2025
    Inventors: Maoxiu ZHOU, Lei GUO, Ke DAI, Chunxu ZHANG, Min CHENG, Xiaoting JIANG, Haipeng YANG
  • Publication number: 20240419505
    Abstract: In an approach for intelligent workload scheduling, a processor groups a plurality of batch jobs based on workload resource requests and dependencies of each batch job resulting in a plurality of groups. A processor schedules the plurality of batch jobs based on the plurality of groups. A processor monitors workload resource usage of system for running the plurality of batch jobs and a plurality of transaction workloads. A processor identifies one or more scheduled transaction workloads will not be able to be completed in under a preset time threshold. A processor reduces a resource quota of one or more batch jobs of the plurality of batch jobs based on type of resource that is needed for the one or more scheduled transaction workloads.
    Type: Application
    Filed: June 17, 2023
    Publication date: December 19, 2024
    Inventors: Guang Han Sui, Mai Zeng, Min Cheng, Peng Hui Jiang
  • Patent number: 12167183
    Abstract: In an image processing method, an image processing device obtains an input image from an image sensor. Each pixel of the input image is either a type-I pixel or a type-II pixel. Each type-I pixel carries a luminance channel value and no color data, and each type-II pixel carries a single color channel value and no luminance data, wherein the single color channel value is a cyan channel value, a magenta channel value, or a yellow channel value. The image processing device generates a target image by performing interpolation based on the luminance channel values and the single color channel values of the pixels of the input image, wherein each pixel in the target image corresponds in location to a pixel in the input image and has three color channel values generated by the interpolation.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: December 10, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Min Cheng, Daolong Tang, Yufeng Dai
  • Patent number: 12163913
    Abstract: An electrochemical cell for sensing gas has added mechanical support for the working electrode to prevent flexure of the working electrode due to pressure differentials. The added mechanical support includes: 1) affixing a larger area of the working electrode to the body of the cell; 2) a gas vent to a cavity of the body to equalize pressures; 3) a rigid electrolyte layer abutting a back surface of the working electrode; 4) infusing an adhesive deep into sides of the porous working electrode to enhance rigidity; 5) supporting opposing surfaces of the working electrode with the rigid package body; and 6) other techniques to make the working electrode more rigid. A bias circuit is also described that uses a controllable current source, an integrator of the varying current, and a feedback circuit for supplying a voltage to the counter electrode and a bias voltage to the reference electrode.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: December 10, 2024
    Assignee: QUALCOMM Technologies, Inc.
    Inventors: Jim Chih-Min Cheng, Eric Paul Lee, Jerome Chandra Bhat
  • Publication number: 20240400846
    Abstract: Aqueous inkjet ink compositions are provided which comprise water, a co-medium, pigment particles, and resin particles, wherein the resin particles comprise a polymerization product of reactants comprising: one or more types of hydrophobic monomers; and one or more types of anionic monomers comprising one or more types of crosslinkable anionic monomers.
    Type: Application
    Filed: May 30, 2023
    Publication date: December 5, 2024
    Inventors: Jing X. Sun, Nienwen Chow, David M. Skinner, Peter V. Nguyen, Chieh-Min Cheng
  • Patent number: 12160990
    Abstract: A semiconductor structure includes a substrate, a common source plane disposed on the substrate, a plurality of memory cells vertically disposed on the substrate and electrically connected to the common source plane, a common source line disposed on the substrate and electrically connected to the common source plane, and an isolation pillar. The common source line extends along a first direction and has a first segment and a second segment. The isolation pillar interposes the first segment and the second segment of the common source line.
    Type: Grant
    Filed: February 23, 2022
    Date of Patent: December 3, 2024
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Jung-Yi Guo, Chun-Min Cheng
  • Publication number: 20240397576
    Abstract: The application provides a wireless communication method and a wireless communication device. A part of payload is pre-fetched from a host to a data buffer under a store-and-forward mode before transmission begins. When data transmission begins, the part of the payload pre-fetched in the data buffer is transmitted to an antenna. A remaining part of the payload is fetched to the data buffer under a cut-through mode for payload transmission, wherein the remaining part of the payload is sent from the data buffer to the antenna for radiation.
    Type: Application
    Filed: May 14, 2024
    Publication date: November 28, 2024
    Inventors: Hao-Hua KANG, Hui-Ping TSENG, Cheng-Ying WU, Chih-Chun KUO, Shu-Min CHENG, Chi-Han HUANG, Yang-Hung PENG, Jyh-Ding HU, Chih-Pin CHU, Chu-Ling CHANG, Yen-Hsiung TSENG, Chi-Fu KOH, Yen CHUANG
  • Publication number: 20240385485
    Abstract: A display panel includes: a first active area and at least one second active area, a substrate; a plurality of sub-pixels located on the substrate, the plurality of sub-pixels being in the first active area, and each of the sub-pixels including a common electrode; grid lines and data lines, at least one of the data lines being located at a junction of the first active area and the second active area; a plurality of first conductive patterns at least in the second active area, and the first conductive patterns being electrically connected to one of the grid lines or the common electrode; and a plurality of second conductive patterns in the second active area and electrically connected to the data line at the junction, orthographic projections of part first conductive patterns on the substrate overlap orthographic projections of the second conductive patterns on the substrate.
    Type: Application
    Filed: September 29, 2022
    Publication date: November 21, 2024
    Applicants: Hefei BOE Display Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Chunxu Zhang, Maoxiu Zhou, Xiaoting Jiang, Min Cheng, Haipeng Yang, Ke Dai, Hui Li
  • Patent number: 12147155
    Abstract: A mask correction method, a mask correction device for double patterning, and a training method for a layout machine learning model are provided. The mask correction method for double patterning includes the following steps. A target layout is obtained. The target layout is decomposed into two sub-layouts, which overlap at a stitch region. A size of the stitch region is analyzed by the layout machine learning model according to the target layout. The layout machine learning model is established according to a three-dimensional information after etching. An optical proximity correction (OPC) procedure is performed on the sub-layouts.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: November 19, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Min-Cheng Yang, Chung-Yi Chiu
  • Publication number: 20240379380
    Abstract: A system and method for generating a gas curtain over an access port of a processing chamber for a semiconductor substrate. A gas flow stabilizer and a gas flow receiver, each including a horizontal flow section and a vertical flow section cooperate to generate a gas curtain that impedes gas, e.g., oxygen, from outside the processing chamber, from flowing into the chamber, for example, when the access port is opened to add/or to remove a workpiece from the processing chamber.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Inventors: Sheng-Chun YANG, Po-Chih HUANG, Chih-Lung CHENG, Yi-Ming LIN, Chen-Hao LIAO, Min-Cheng CHUNG
  • Patent number: 12137078
    Abstract: Disclosed herein are system, method, apparatus, and computer program product embodiments for dynamic mitigation of CGN IPv4 address provisioning for network gateways when adverse conditions are in effect. A network gateway may be provisioned with a shared WAN IP address from a pool of IP addresses designated for Carrier Grade Network Address Translation (CGN) and configured to detect the occurrence of an adverse condition for a connection provisioned the shared WAN IP address. Upon detecting an adverse condition, the network gateway may send a request for a new IP address to a DHCP server configured to recognize flags indicating an adverse condition. The DHCP server may then provision the gateway with a new public IP address.
    Type: Grant
    Filed: May 13, 2022
    Date of Patent: November 5, 2024
    Assignee: CSC Holdings, LLC
    Inventors: John Pomeroy, Chris Zydel, Min Cheng David Wang
  • Publication number: 20240357827
    Abstract: A ferroelectric memory structure including a substrate, first and second conductive lines, first and second dielectric layers, a channel pillar, a gate pillar, and a ferroelectric material layer is provided. The first conductive line is located on the substrate. The first dielectric layer is located on the first conductive line. The channel pillar is located on the first conductive line and in the first dielectric layer. The second conductive line is located on the first dielectric layer and the channel pillar. The gate pillar passes through the second conductive line and is located in the channel pillar. The second dielectric layer is located between the gate pillar and the first conductive line, between the gate pillar and the channel pillar, and between the gate pillar and the second conductive line. The ferroelectric material layer is located between the gate pillar and the second dielectric layer.
    Type: Application
    Filed: July 20, 2023
    Publication date: October 24, 2024
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Jyun-Hong Shih, Min-Cheng Chen
  • Publication number: 20240347203
    Abstract: Methods and computer-implemented methods are used to predict a risk of cardiovascular disease by using a machine learning mode to analyze a relationship between the occurrence of cardiovascular disease and the health data of patients.
    Type: Application
    Filed: April 12, 2023
    Publication date: October 17, 2024
    Applicants: Taipei Veterans General Hospital, Academia Sinica, National Taiwan University
    Inventors: Hao-Min Cheng, Yeong-Sung Lin, Yennun Huang, Chiu-Han Hsiao, Po-Chun Yu, Chia-Ying Hsieh, Wei-Lun Chang
  • Publication number: 20240327925
    Abstract: Described herein are methods and kits for detecting the presence or absence of gene dysregulations such as those arising from gene fusions and/or chromosomal abnormalities, e.g. translocations, insertions, inversions and deletions. The methods, compositions and kits are useful for detecting mutations that cause the differential expression of a 5? portion of a target gene relative to the 3? region of the target gene. The average expression of the 5? portion of the target gene is compared with the average expression of the 3? portion of the target gene to determine an intragenic differential expression (IDE). The IDE can then be used to determine if a dysregulation or a particular disease (or susceptibility to a disease) is present or absent in a subject or sample.
    Type: Application
    Filed: February 26, 2024
    Publication date: October 3, 2024
    Applicant: Quest Diagnostics Investments LLC
    Inventor: Shih-Min CHENG
  • Publication number: 20240328020
    Abstract: A method for recovering valuable metal elements from a copper-containing metallic material includes steps of: (a) immersing an anode and the copper-containing metallic material serving as a cathode into an electrolyte solution having one of an acidic pH and an alkaline pH; and (b) providing a predetermined voltage to the anode and the cathode such that an electrolysis process conducted under the predetermined voltage on the cathode forms a gaseous film surrounding the cathode, and then the gaseous film is broken down to permit generation of a plasma in the electrolyte solution so as to obtain a solid copper metal or a solid copper oxide that precipitates from the electrolyte solution, and ionic impurities that dissolve in the electrolyte solution.
    Type: Application
    Filed: June 27, 2023
    Publication date: October 3, 2024
    Inventors: Chih-Huang LAI, Zheng-Yu CHEN, Tzu-Min CHENG
  • Publication number: 20240325994
    Abstract: A mixer includes a shaft and an agitator coupled to the shaft. The shaft and the agitator are configured to rotate together to mix a liquid composition. The mixer also includes a sleeve positioned around the shaft. The sleeve forms a gap between the shaft and the sleeve. The sleeve is positioned in the liquid composition such that the liquid composition fills the gap up to the surface of the liquid composition in the gap to form a liquid seal between the shaft and the sleeve that minimizes an amount of air that penetrates into the liquid composition outside the gap during rotation of the shaft and the agitator.
    Type: Application
    Filed: March 29, 2023
    Publication date: October 3, 2024
    Applicant: XEROX CORPORATION
    Inventors: Lanhui Zhang, Genggeng Qi, Brian J. Marion, Troy Brown, Yu Qi, Chieh-Min Cheng
  • Publication number: 20240321168
    Abstract: The present disclosure provides a display substrate and a display device. The display substrate includes a base substrate and a driving circuit arranged on the base substrate. The driving circuit includes multiple denoising transistors and multiple transistors for driving, and the denoising transistors are electrically connected to a pull-up node. A length of a channel of each of at least a part of the denoising transistors is a first length L1, a length of a channel of each of at least a part of the multiple transistors for driving is a second length L2, and the first length L1 is not equal to the second length L2.
    Type: Application
    Filed: March 21, 2022
    Publication date: September 26, 2024
    Applicants: HEFEI BOE DISPLAY TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Qi Liu, Chunxu Zhang, Jiantao Liu, Lei Guo, Maoxiu Zhou, Min Cheng, Xiaoting Jiang
  • Patent number: 12101941
    Abstract: A ferroelectric memory structure including a substrate, a ferroelectric capacitor structure, and a switch device is provided. The ferroelectric capacitor structure is disposed on the substrate. The ferroelectric capacitor structure includes at least one first electrode, first dielectric layers, a second electrode, and a ferroelectric material layer. The at least one first electrode and the first dielectric layers are alternately stacked. The second electrode penetrates through the first electrode. The ferroelectric material layer is disposed between the first electrode and the second electrode. The switch device is electrically connected to the ferroelectric capacitor structure.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: September 24, 2024
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Shou-Zen Chang, Ming-Han Liao, Min-Cheng Chen, Hiroshi Yoshida
  • Publication number: 20240312930
    Abstract: A semiconductor package includes a substrate, a semiconductor die, a ring structure and a lid. The semiconductor die is disposed on the substrate. The ring structure is disposed on the substrate and surrounds the semiconductor die, where a first side of the semiconductor die is distant from an inner sidewall of the ring structure by a first gap, and a second side of the semiconductor die is distant from the inner sidewall of the ring structure by a second gap. The first side is opposite to the second side, and the first gap is less than the second gap. The lid is disposed on the ring structure and has a recess formed therein, and the recess overlaps with the first gap in a stacking direction of the ring structure and the lid.
    Type: Application
    Filed: May 24, 2024
    Publication date: September 19, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Ming Ching, Shu-Shen Yeh, Chien-Hung Chen, Hui-Chang Yu, Yu-Min Cheng
  • Patent number: D1046510
    Type: Grant
    Filed: June 27, 2024
    Date of Patent: October 15, 2024
    Inventor: Min Cheng