Abstract: A semiconductor structure includes a substrate, a common source plane disposed on the substrate, a plurality of memory cells vertically disposed on the substrate and electrically connected to the common source plane, a common source line disposed on the substrate and electrically connected to the common source plane, and an isolation pillar. The common source line extends along a first direction and has a first segment and a second segment. The isolation pillar interposes the first segment and the second segment of the common source line.

Abstract: The application provides a wireless communication method and a wireless communication device. A part of payload is pre-fetched from a host to a data buffer under a store-and-forward mode before transmission begins. When data transmission begins, the part of the payload pre-fetched in the data buffer is transmitted to an antenna. A remaining part of the payload is fetched to the data buffer under a cut-through mode for payload transmission, wherein the remaining part of the payload is sent from the data buffer to the antenna for radiation.

Abstract: A display panel includes: a first active area and at least one second active area, a substrate; a plurality of sub-pixels located on the substrate, the plurality of sub-pixels being in the first active area, and each of the sub-pixels including a common electrode; grid lines and data lines, at least one of the data lines being located at a junction of the first active area and the second active area; a plurality of first conductive patterns at least in the second active area, and the first conductive patterns being electrically connected to one of the grid lines or the common electrode; and a plurality of second conductive patterns in the second active area and electrically connected to the data line at the junction, orthographic projections of part first conductive patterns on the substrate overlap orthographic projections of the second conductive patterns on the substrate.

Abstract: A mask correction method, a mask correction device for double patterning, and a training method for a layout machine learning model are provided. The mask correction method for double patterning includes the following steps. A target layout is obtained. The target layout is decomposed into two sub-layouts, which overlap at a stitch region. A size of the stitch region is analyzed by the layout machine learning model according to the target layout. The layout machine learning model is established according to a three-dimensional information after etching. An optical proximity correction (OPC) procedure is performed on the sub-layouts.

Abstract: A system and method for generating a gas curtain over an access port of a processing chamber for a semiconductor substrate. A gas flow stabilizer and a gas flow receiver, each including a horizontal flow section and a vertical flow section cooperate to generate a gas curtain that impedes gas, e.g., oxygen, from outside the processing chamber, from flowing into the chamber, for example, when the access port is opened to add/or to remove a workpiece from the processing chamber.

Abstract: Disclosed herein are system, method, apparatus, and computer program product embodiments for dynamic mitigation of CGN IPv4 address provisioning for network gateways when adverse conditions are in effect. A network gateway may be provisioned with a shared WAN IP address from a pool of IP addresses designated for Carrier Grade Network Address Translation (CGN) and configured to detect the occurrence of an adverse condition for a connection provisioned the shared WAN IP address. Upon detecting an adverse condition, the network gateway may send a request for a new IP address to a DHCP server configured to recognize flags indicating an adverse condition. The DHCP server may then provision the gateway with a new public IP address.

Abstract: A ferroelectric memory structure including a substrate, first and second conductive lines, first and second dielectric layers, a channel pillar, a gate pillar, and a ferroelectric material layer is provided. The first conductive line is located on the substrate. The first dielectric layer is located on the first conductive line. The channel pillar is located on the first conductive line and in the first dielectric layer. The second conductive line is located on the first dielectric layer and the channel pillar. The gate pillar passes through the second conductive line and is located in the channel pillar. The second dielectric layer is located between the gate pillar and the first conductive line, between the gate pillar and the channel pillar, and between the gate pillar and the second conductive line. The ferroelectric material layer is located between the gate pillar and the second dielectric layer.

Abstract: Methods and computer-implemented methods are used to predict a risk of cardiovascular disease by using a machine learning mode to analyze a relationship between the occurrence of cardiovascular disease and the health data of patients.

Abstract: A mixer includes a shaft and an agitator coupled to the shaft. The shaft and the agitator are configured to rotate together to mix a liquid composition. The mixer also includes a sleeve positioned around the shaft. The sleeve forms a gap between the shaft and the sleeve. The sleeve is positioned in the liquid composition such that the liquid composition fills the gap up to the surface of the liquid composition in the gap to form a liquid seal between the shaft and the sleeve that minimizes an amount of air that penetrates into the liquid composition outside the gap during rotation of the shaft and the agitator.

Abstract: A method for recovering valuable metal elements from a copper-containing metallic material includes steps of: (a) immersing an anode and the copper-containing metallic material serving as a cathode into an electrolyte solution having one of an acidic pH and an alkaline pH; and (b) providing a predetermined voltage to the anode and the cathode such that an electrolysis process conducted under the predetermined voltage on the cathode forms a gaseous film surrounding the cathode, and then the gaseous film is broken down to permit generation of a plasma in the electrolyte solution so as to obtain a solid copper metal or a solid copper oxide that precipitates from the electrolyte solution, and ionic impurities that dissolve in the electrolyte solution.

Abstract: Described herein are methods and kits for detecting the presence or absence of gene dysregulations such as those arising from gene fusions and/or chromosomal abnormalities, e.g. translocations, insertions, inversions and deletions. The methods, compositions and kits are useful for detecting mutations that cause the differential expression of a 5? portion of a target gene relative to the 3? region of the target gene. The average expression of the 5? portion of the target gene is compared with the average expression of the 3? portion of the target gene to determine an intragenic differential expression (IDE). The IDE can then be used to determine if a dysregulation or a particular disease (or susceptibility to a disease) is present or absent in a subject or sample.

Abstract: The present disclosure provides a display substrate and a display device. The display substrate includes a base substrate and a driving circuit arranged on the base substrate. The driving circuit includes multiple denoising transistors and multiple transistors for driving, and the denoising transistors are electrically connected to a pull-up node. A length of a channel of each of at least a part of the denoising transistors is a first length L1, a length of a channel of each of at least a part of the multiple transistors for driving is a second length L2, and the first length L1 is not equal to the second length L2.

Abstract: A ferroelectric memory structure including a substrate, a ferroelectric capacitor structure, and a switch device is provided. The ferroelectric capacitor structure is disposed on the substrate. The ferroelectric capacitor structure includes at least one first electrode, first dielectric layers, a second electrode, and a ferroelectric material layer. The at least one first electrode and the first dielectric layers are alternately stacked. The second electrode penetrates through the first electrode. The ferroelectric material layer is disposed between the first electrode and the second electrode. The switch device is electrically connected to the ferroelectric capacitor structure.

Abstract: A semiconductor package includes a substrate, a semiconductor die, a ring structure and a lid. The semiconductor die is disposed on the substrate. The ring structure is disposed on the substrate and surrounds the semiconductor die, where a first side of the semiconductor die is distant from an inner sidewall of the ring structure by a first gap, and a second side of the semiconductor die is distant from the inner sidewall of the ring structure by a second gap. The first side is opposite to the second side, and the first gap is less than the second gap. The lid is disposed on the ring structure and has a recess formed therein, and the recess overlaps with the first gap in a stacking direction of the ring structure and the lid.

Abstract: A method of operating a processing apparatus is provided. The method includes placing a substrate storage container on a load port. The method includes matching a plurality of positioning holes are on a base board of the substrate storage container with a plurality of positioning pins on a base frame of the load port. The method also includes transferring a substrate from the substrate storage container when the substrate storage container is placed on the base frame.

Abstract: Automatic process generation and recommendation can include extracting, in real time, features from user input to a computer. The features extracted can be compared with recorded features corresponding to a prior behavior. A user-intended action can be predicted in response to a match between the features extracted and the features corresponding to the prior behavior. A sequence of processor-executable actions corresponding to the prior behavior can be generated.

Abstract: The present disclosure is related to systems and methods for image processing. The method includes obtaining an image including a plurality of pixels. The method includes determining at least one brightness parameter based on the brightness values of the plurality of pixels. The method includes obtaining an image processing algorithm including at least one image processing parameter. The method includes determining a value of the at least one image processing parameter based on the at least one brightness parameter. The method includes generating a target image by processing the image according to the image processing algorithm upon the value of the at least one image processing parameter.

Abstract: Provided is an optical sensor for monitoring pulse waveform and blood pressure of a subject. The optical sensor may be manufactured with compact structure, low profile, low cost, and exhibits benefits of disposability, easy to apply, immunity to electro-magnetic interference, high sensitivity, having minimal affect towards sense of touch, maintains patient safety, and supportive of accurate real-time measurements for the clinician. Therefore, pulse waveform and blood pressures of a subject may be faithfully monitored continuously throughout day and night, so as to provide abundant prognostic information while avoiding interference in normal daily activity of the subject. Also provided is a system utilizing the optical sensors for monitoring pulse waveform and blood pressure of a subject.

Abstract: The present disclosure relates to the field of display technologies and, in particular to a display panel and an electronic device. The display panel comprises: Q rows of first scanning line groups arranged sequentially along a column direction; M columns of second scanning line groups arranged sequentially along a row direction; and at least one gate drive circuit, located on a side of the Q-th row of the first scanning line groups away from the (Q?1)-th row of the first scanning line groups. Each gate drive circuit comprises Q columns of shift register unit groups cascaded in stages. The q-th stage of the shift register unit groups is connected with the q-th row of the first scanning line groups through at least one column of the second scanning line groups. M?Q>1, 1?q?Q, and M, N, Q, q are all positive integers.