Abstract: A method of forming an ultra-thin wafer level stack package and structure thereof are provided. The method includes providing a first wafer having a plurality of base chips thereon, selectively binding the first wafer to a second substrate, lapping the first wafer to reduce its thickness, dicing the lapped first wafer, bonding a plurality stack chips to each base chip and packaging the base chip with the bonded stack chips to form an IC package. Thus, each IC package comprises at least a base chip and a stack chip. The IC package has a size almost identical to the base chip and a thickness a little larger than the combined thickness of the base chip and the stack chip. If a known good die inspection of the base chips and stack chips are carried out prior to wafer level packaging, overall yield of the IC package is increased.

Abstract: A structure of an ultra-thin wafer level stack package is provided. A method for manufacturing the structure includes providing a first wafer having a plurality of base chips thereon, selectively binding the first wafer to a second substrate, lapping the first wafer to reduce its thickness, dicing the lapped first wafer, bonding a plurality stack chips to each base chip and packaging the base chip with the bonded stack chips to form an IC package. Thus, each IC package comprises at least a base chip and a stack chip. The IC package has a size almost identical to the base chip and a thickness a little larger than the combined thickness of the base chip and the stack chip. If a known good die inspection of the base chips and stack chips are carried out prior to wafer level packaging, overall yield of the IC package is increased.

Abstract: The present invention relates to a method for manufacturing a wafer level chip scale package structure including the following steps. After providing a glass substrate and a wafer comprising a plurality of chips, the active surface of the wafer is connected to the top surface of the glass substrate. The wafer is connected with the glass substrate through either bumps or pads thereon. After drilling the glass substrate to form a plurality of through holes, a plating process is performed to form a plurality of via plugs in the through holes. Afterwards, a singulation step is performed and a plurality of chip scale package structures is obtained.

Abstract: A semiconductor package including a flexible multichip module having multiple chips on flexible appendages with the flexible appendages folded so that the semiconductor chips are arranged in aligned and stacked positions.

Abstract: The present invention relates to a method for manufacturing a wafer level chip scale package structure including the following steps. After providing a glass substrate and a wafer comprising a plurality of chips, the active surface of the wafer is connected to the top surface of the glass substrate. The wafer is connected with the glass substrate through either bumps or pads thereon. After drilling the glass substrate to form a plurality of through holes, a plating process is performed to form a plurality of via plugs in the through holes. Afterwards, a singulation step is performed and a plurality of chip scale package structures is obtained.

Abstract: A method of repairing white spots on a liquid crystal display (LCD) panel and a LCD pane thereof are provided. The method includes the steps of detecting any white spot on the liquid crystal display after the manufacturing process and repairing the white spot by coating a repairing spot on the surface of the panel above the white spot. Furthermore, the repairing spot may have a micro-lens structure. Therefore, the repairing spot can absorb, diverge or scatter the light from the white spot. Alternatively, the repairing spot can also change the optical pathway or the polarity or the polarity distribution of the light from the white spot so that an analyzer or a polarizer can block the light from the white spot to produce a dark spot.

Abstract: A system-in-package (SIP) structure is described, including stacked circuit/insulator composite layers, bumps and a cover plate. Each circuit/insulator composite layer is lifted off from a semiconductor-on-insulator (SOI) substrate, including the insulator of the SOI substrate and a circuit layer based on the semiconductor of the SOI substrate. The circuit layer of a circuit/insulator composite layer is electrically coupled with the circuit layer of the underlying circuit/insulator composite layer. The bumps are disposed on the lower surface of the bottom circuit/insulator composite layer, electrically coupled with the circuit layer of the bottom circuit/insulator composite layer. The cover plate is disposed on the top circuit/insulator composite layer.

Abstract: A semiconductor package including a flexible multichip module having multiple chips on flexible appendages with the flexible appendages folded so that the semiconductor chips are arranged in aligned and stacked positions.

Abstract: The chip package and the process thereof are disclosed. In the chip package, a rigid cover is disposed on the active surface of the chip to protect the active surface of the chip and enhance the structural strength of the chip package. Further, if the material of the rigid cover is a thermal conductive material such as Cu or Al alloy, the heat-spread ability of the chip package can be enhanced. If the rigid cover is made of an electrical conductive material and electrically connected to the ground, the electromagnetic interference (EMI) to the chip package can be reduced. It should be noted that the chip packaging process can form a plurality of the terminal pads on the backside of the chip so that the chip package can be connected to the PCB or substrate via these terminal pads.

Abstract: A method of forming an ultra-thin wafer level stack package and structure thereof are provided. The method includes providing a first wafer having a plurality of base chips thereon, selectively binding the first wafer to a second substrate, lapping the first wafer to reduce its thickness, dicing the lapped first wafer, bonding a plurality stack chips to each base chip and packaging the base chip with the bonded stack chips to form an IC package. Thus, each IC package comprises at least a base chip and a stack chip. The IC package has a size almost identical to the base chip and a thickness a little larger than the combined thickness of the base chip and the stack chip. If a known good die inspection of the base chips and stack chips are carried out prior to wafer level packaging, overall yield of the IC package is increased.

Abstract: A method of repairing white spots on a liquid crystal display (LCD) panel and a LCD pane thereof are provided. The method includes the steps of detecting any white spot on the liquid crystal display after the manufacturing process and repairing the white spot by coating a repairing spot on the surface of the panel above the white spot. Furthermore, the repairing spot may have a micro-lens structure. Therefore, the repairing spot can absorb, diverge or scatter the light from the white spot. Alternatively, the repairing spot can also change the optical pathway or the polarity or the polarity distribution of the light from the white spot so that an analyzer or a polarizer can block the light from the white spot to produce a dark spot.

Abstract: A digital cellular phone system by which a user can set up a group and a cellular phone applied thereto are disclosed. When a registration was sent to the digital cellular phone system, it can be determined whether a member of the group is within the communication range of a same or neighboring base station of a user. When a member is within the communication range of a same base station of the user, the user is informed by short message service. In addition, when the member is within the communication range of a same base station of the user, the user can register for the location information of the member and the distance between the user and the member.

Abstract: An integrated audio/video sensor is provided. The integrated sensor comprises an image-receiving module for sensing a light of an image, a sound-receiving module for sensing a sound and a signal-transforming module for integrating image and sound signals into an audio/video signal. The integrated sensor integrates image and sound together simultaneously and synchronously. Furthermore, the integrated sensor can be connected directly to an image-processing system. The integrated sensor not only provides excellent synchronization of audio and video signals, but also reduces the size and cost of producing the integrated sensor as well.

Abstract: A software copyright protection system, method, chip and peripheral subsystem is provided. In one aspect of this invention, a smart security identity (SID) integrated circuit (IC) is used for registering a legal user. To become an authorized users of a particular software program, a software serial number and a communication equipment serial number must be submitted to the smart SID IC in a registration process to obtain a legal inspection code. The smart SID IC not only serves as a hardware serial number built-in module, but also reports to the software producer any illegal software registration attempts.

Abstract: A semiconductor die and an associated low resistance interconnect located primarily on the bottom surface of such die is disclosed. This arrangement provides a flexible packaging structure permitting easy interconnected with other integrated circuits; in this manner, a number of such circuits can be stacked to create high circuit density multi-chip modules. A process for making the device is further disclosed. To preserve structural integrity of a wafer containing such die during manufacturing, a through-hole via formed as part of the interconnect is filled with an inert material during operations associated with subsequent active device formation on such die.

Abstract: An architecture for wafer scale memories and a placement method replaces defective chips with spare chips in a memory module so as to provide minimum critical signal delay. The SDRAM memory chips are classified into normal chips and spare chips, where the normal chips are formed into groups such as rows or columns, and the spare chips are used to replace defective normal chips. A delay model for metal lines and vias is used to compute the signal delay for placement and routing. The placement problem is modeled as a bipartite graph and solved using a branch and bound algorithm to obtain a chip replacement configuration having the shortest critical signal delay. Also described is a hierarchical routing approach, which classifies the signals into different types and levels of signals.

Abstract: A universal power supply system has a device circuit, a universal power supply, and a standard interface unit coupled between the device circuit, and the universal power supply, whereby a required power is supplied to the electronic product. The device circuit includes a device ID code unit to provide an ID code, and a power input interface by which the required power can be inputted to the device circuit. The universal power supply includes a voltage supply unit, a device ID detecting unit that can detect the device ID code through the standard interface, and a voltage control unit to control the voltage supply unit for providing the required power type through the standard interface.

Abstract: A method of fabricating a direct contact through hole type wafer. Devices and contact plugs are formed in one side of a silicon-on-insulator substrate, and multilevel interconnects are formed over the side of the silicon-on-insulator substrate. The multilevel interconnects are coupled with the devices and the contact plugs. Bonding pads, which couples with the multilevel interconnects, are formed over the multilevel interconnects. An opening is formed on the other side of the silicon-on-insulator substrate to expose the contact plugs. An insulation layer, a barrier layer and a metal layer are formed in sequence in the opening. Bumps are formed on the bonding pads and the metal layer, respectively.

Abstract: A method of fabricating a direct contact through hole type wafer. Devices and contact plugs are formed in one side of a silicon-on-insulator substrate, and multilevel interconnects are formed over the side of the silicon-on-insulator substrate. The multilevel interconnects are coupled with the devices and the contact plugs. Bonding pads, which couples with the multilevel interconnects, are formed over the multilevel interconnects. An opening is formed on the other side of the silicon-on-insulator substrate to expose the contact plugs. An insulation layer, a barrier layer and a metal layer are formed in sequence in the opening. Bumps are formed on the bonding pads and the metal layer, respectively.

Abstract: A direct contact through hole type wafer structure. Both sides of a wafer have devices and contacts. The contacts are coupled with the devices. Bumps are formed on the contacts, respectively.