Abstract: A preburn-in DRAM module circuit board is provided, which allows a plurality of DRAM modules to be constructed directly thereon, and which can be directly connected to a large burn-in oven so as to perform a burn-in process concurrently on the DRAM modules mounted thereon to check for any defected IC chips that are to be reworked. After the burn-in process, each of the DRAM modules can be cut apart from the circuit board to serve as a single memory module. The preburn-in DRAM module circuit board allows the manufacturing process for the DRAM modules to be reduced in schedule and manufacturing cost. Material cost can also be saved since the burn-in circuit and the module circuit are arranged on the same circuit board.

Abstract: A wafer level package structure. The method of forming the wafer level package structure includes covering a silicon chip having a plurality of integrated circuit devices thereon with an insulation layer. Next, a plurality of bonding pads is formed on the periphery of the silicon chip above the insulation layer. The bonding pads are formed such that each bonding pad is electrically connected to the terminal of an integrated circuit device. Thereafter, a passivation layer is deposited over the insulation layer and the bonding pads, and then openings that expose a portion of the bonding pad are formed. Subsequently, a metallic layer is formed on the sidewalls and the exposed bonding pad area. The metallic layer also extends over the passivation layer in the neighborhood of the opening and towards the edge of the wafer chip. Next, a layer of packaging material is deposited over the passivation layer. Finally, a metallic bump is formed over the exposed metallic layer lying above each opening.

Abstract: A direct contact through hole type wafer structure. Both sides of a wafer have devices and contacts. The contacts are coupled with the devices. Bumps are formed on the contacts, respectively.

Abstract: A direct contact through hole type wafer structure. Both sides of a wafer have devices and contacts. The contacts are coupled with the devices. Bumps are formed on the contacts, respectively.

Abstract: A multi-chip chip scale package. The package has a film carrier whereby two chips with different sizes can be disposed on the same film carrier. A flip chip technique is used to arrange each chip on each side of the film carrier face to face. A bump is formed on each chip to electrically connect with the film carrier. An insulation material is filled in between the chips to leave one side of each chip exposed. The conductive wires of the film carrier are connected to the chips directly.

Abstract: A face-to-face multi-chip package comprises a lead frame comprising at least a die pad and a plurality of leads, wherein the leads further comprise a plurality of inner leads and a plurality of outer leads. The package further comprises at least three chips, each having a surface comprising a plurality of pads. The chips are disposed with the surfaces comprising the pads face to face. A plurality of bumps are disposed on some of the pads to electrically connect the chips. A plurality of electrical conductors connects predetermined ones of the pads to the inner leads; and an insulation material fully or partially seals the die pad, the chips and the inner leads.

Abstract: A multi-chip chip scale package. A film carrier is in use. Two chips with different sizes can be disposed on the same film carrier. The flip chip technique is used to arrange each chip on each side of the film carrier face to face. A bump is formed on each chip to electrically connect with the film carrier. An insulation material is infilled between the chips to leave one side of each chip exposed. The conductive wires of the film carrier are connected with the chip directly without going through other carrier.

Abstract: A wafer level IC structure and a method of manufacturing this wafer level IC structure are proposed, which can help increase the yield of the IC manufacture. The wafer level IC structure is constructed on a semiconductor wafer which is defined into a plurality of discrete IC blocks on the wafer, each IC block being used to form a plurality of IC components such as memory cells. A multi-layer interconnect structure is formed to electrically interconnect these IC components in each of the IC blocks. A first testing and repair process is then perform to disconnect any inoperative IC components from active use. This completes the fabrication stage of the manufacture process. In the subsequent packaging stage, a redistribution line structure is formed to interconnect the discrete IC blocks into an integral functional unit. A second testing and repair process is then perform to disconnect any inoperative IC blocks from active use.

Abstract: A cascade-type chip module. A laminate substrate having contacts is provided. Chips suitable for the cascade-type module are provided. Each chip includes a redistribution layer having a first region and a second region and bump contacts over the redistribution layer. A layout of the bump contacts coupling with the first region of the redistribution layer is an image rotationally symmetrical to the layout of those coupling with the second region of the redistribution layer, and each of the bump contacts coupling with the first region is coupled with a corresponding bump contact coupling with the second region through the redistribution layer. The chips are divided into a first group and a second group; the first group is stacked on the second group such that the first region of each chip of the first group is aligned with the second region of each chip of the second group and the second region of each chip of the first group is aligned with the first region of each chip of the second group.

Abstract: A package-free bonding pad structure on a silicon chip that includes a plurality of metal pads on the upper surface of the silicon chip and a passivation layer covering the upper surface of the silicon chip. The passivation layer has a plurality of open cavities directly above the metal pad areas for exposing a portion of each metal pad. Diameter of the open cavity gets smaller on approaching the upper surface of the passivation layer and grows bigger in the neighborhood of the metal pad area.

Abstract: A repairable memory module, such as a DRAM (dynamic random access memory) or a flash memory module, and a method of repairing memory modules are proposed. Based on the repairable memory module, any failed memory ICs in the module that are found before shipment or after use can be repaired through the use of a backup memory IC. Fundamentally, when any failed memory ICs are found in the module, a set of zero-ohm resistors are used to short-circuit a number of selected pairs of jumping pads to thereby redirect the connections to the I/O (input/output) and column-address strobe pins on the failed memory IC instead to the same nominal pins on the backup memory IC. This allows the function of the failed ICs to be instead performed by the backup memory chip.

Abstract: A system for maintaining the security of information transmitted between facsimile machines includes a transmitting/receiving facsimile machine for receiving input sheets having an encryption zone; an image sensor for detecting the encryption zones; an encryption device for scrambling messages that appear within an encryption zone. Further the system includes means for sensing encryption zones on transmitted messages and for decoding messages that have been scrambled within the encryption zones.