Abstract: Transmitting antennas and receiving antennas are arranged such that a plurality of virtual antennas have the same position in a time-division-multiplexed (TDM) frequency modulated continuous wave (FMCW) radar apparatus. At least three peculiar chirps, at least one of which is included in a chirp loop of each of waveform signals transmitted by the plurality of virtual antennas having the same position, are respectively positioned in consecutive time slots and have different periods. A Doppler frequency may be uniquely determined from phase difference values between the at least three peculiar chirps respectively positioned in consecutive time slots measured from FMCW radar signals received at the plurality of virtual antennas.

Abstract: An embodiment provides a sensing device comprising: a magnet; a first collector disposed to correspond to a path along which the magnet moves; and a first sensor disposed at one side of the first collector, wherein the first collector comprises a first leg part and a second leg part, the first leg part and the second leg part each comprise a facing surface disposed to face the magnet, and the sensing device comprises an area in which a gap between the first leg part and the second leg part increases along a direction from one side toward the other side thereof or an area in which the facing surface of each of the first leg part and the second leg part has a width decreasing along a direction from one side toward the other side thereof. Accordingly, the sensing device can reduce an effect of an external magnetic field to improve sensing accuracy.

Abstract: A semiconductor device, and a method of manufacturing the same, includes a gate stack including a plurality of conductive lines extending in a first horizontal direction, a first slit and a second slit passing through the gate stack in a vertical direction and extending in the first horizontal direction, and a plurality of cell plugs extending in the vertical direction orthogonal to the first horizontal direction in the gate stack between the first slit and the second slit. Each of the first slit and the second slit includes a first portion extending in a diagonal direction between the first horizontal direction and a second horizontal direction orthogonal to the first horizontal direction, and a second portion extending in the first horizontal direction.

Abstract: A substrate treating apparatus in which foreign substances are reduced by using a foreign substance collecting unit includes a magnetic structure. The substrate treating apparatus includes a roller configured to be disposed on a rail extending in a first direction and attached to a side surface of a carrier unit to move along the rail, and a foreign substance collecting unit installed on the side surface of the carrier unit, moving together with the roller, and configured to be spaced apart from the rail when the roller is disposed on the rail, wherein the foreign substance collecting unit includes a magnetic structure for adsorbing foreign magnetic substances using a magnetic force, and a case surrounding the magnetic structure.

Abstract: A chip on film (COF) package in which a predetermined driving integrated circuit (IC) is mounted includes a wiring structure connected to the driving IC, and a test pad connected to the wiring structure, wherein the test pad includes a base film divided into a first region and a second region, and a conductive layer located in the first region, and the second region is surrounded by the first region in a plan view.

Abstract: Provided is a display device comprising a display panel, a metal plate on a bottom surface of the display panel, the metal plate including a first surface facing the bottom surface of the display panel and a second surface opposite to the one surface, and a fingerprint sensor overlappingly disposed on the second surface of the metal plate, wherein the metal plate includes an indentation groove recessed in a direction toward the first surface from the second surface of the metal plate, and the fingerprint sensor is disposed on the second surface of the metal plate on which the indentation groove is formed.

Abstract: A negative electrode for a lithium secondary battery includes: a negative electrode active layer provided on at least one surface of a negative electrode current collector, and including a negative electrode active material; and a coating layer disposed on the negative electrode active layer. The coating layer contains silicon-containing particles, aluminum-containing particles and a dispersant, and a volume resistance of the coating layer is about 1.0×10?4 ?·cm to 1.0 ?·cm.

Abstract: A source driver IC capable of cancelling an output offset is provided. The source driver IC comprises a reception circuit configured to receive an input data packet from a timing controller when operating in a normal mode and obtain an image data and a first clock signal from the input data packet, a control circuit configured to receive and output the image data and the first clock signal from the reception circuit when operating in the normal mode. The control circuit is configured to receive and output a second clock signal from the timing controller when operating in a low power mode. The source driver IC further comprises an output buffer circuit configured to output a data voltage related to the image data when operating in the normal mode and maintain an output of the data voltage when operating in the low power mode.

Abstract: A semiconductor device includes a substrate. An active pattern is on the substrate and extends in a first horizontal direction. First to third nanosheets are sequentially stacked on the active pattern and are spaced apart from each other in a vertical direction. A gate electrode is on the active pattern and extends in a second horizontal direction. The gate electrode surrounds each of the first to third nanosheets. A source/drain region is on the active pattern on at least one side of the gate electrode. An interlayer insulating layer covers the source/drain region. A source/drain contact penetrates the interlayer insulating layer in the vertical direction and is connected to the source/drain region. At least a portion of the interlayer insulating layer is disposed between sidewalls of the source/drain contact and the source/drain region in the first horizontal direction and overlaps sidewalls of the third nanosheet along the first horizontal direction.

Abstract: Proposed are a substrate processing method and a substrate processing apparatus. A substrate processing method according to an embodiment is for etching a thin film formed on a substrate at the atomic layer level, and includes a surface modification step of modifying a surface of the thin film by supplying a first gas including oxygen (O) to a processing space of a chamber in which the substrate is placed, a first purge step of removing the first gas remaining in the processing space by supplying a purge gas to the processing space, an etching step of etching the modified thin film by supplying a CHF3 gas to the processing space, and a second purge step of removing the CHF3 gas remaining in the processing space by supplying the purge gas to the processing space.

Abstract: Proposed are thermal processing apparatus, thermal processing method, and substrate treatment equipment, in which particle generation and damage to a substrate in the cooling process of the substrate can be prevented. The thermal processing apparatus includes a chamber having a processing zone therein, a plurality of chuck pins configured to support a substrate and move up or down individually, a heater configured to provide heat energy to the processing zone, a fluid supply port configured to supply a fluid to the processing zone, a fluid discharge port configured to discharge the fluid remaining in the processing zone to the outside, and a controller configured to control a treatment process of the substrate.

Abstract: A semiconductor device may include: a gate structure including insulating layers and conductive layers alternately stacked; first supports located in the gate structure, each first support including a second channel layer; second supports located in the gate structure, each second support including a barrier layer; and contact structures extending between the second supports through the gate structure, wherein each contact structure is connected to a corresponding conductive layer.

Abstract: Proposed are a substrate processing method and a substrate processing apparatus. A substrate processing method according to an embodiment is for etching a thin film formed on a substrate at the atomic layer level, and includes a surface modification step of modifying a surface of the thin film by supplying a first gas including chlorine (Cl) to a processing space of a chamber in which the substrate is placed, a first purge step of removing the first gas remaining in the processing space by supplying a purge gas to the processing space, an etching step of etching the modified thin film by supplying a second gas including acetylacetone (Hacac) to the processing space, and a second purge step of removing the second gas remaining in the processing space by supplying the purge gas to the processing space.

Abstract: The present disclosure relates to a removable filter system for removably coupling a filter unit to an air supply unit provided in a boiler. The filter unit is detachably coupled to the air supply unit, so that after removing the contaminated filter unit coupled to the air supply unit, a new filter unit can be coupled to the air supply unit or the existing filter unit can be reused after removing contaminants remaining in the filter.

Abstract: In a method of manufacturing a semiconductor device, an additional, induced-stress-limiting structure may be provided on a surface, which opposes stress that can be induced in a semiconductor device during its manufacturing processes. Such a stress compensation layer may be formed on a surface to compensate a stress applied to the rest of structure.

Abstract: A memory device includes: a memory cell array including a plurality of cell plugs; a first slit isolating the memory cell array into a plurality of memory regions, the first slit extending in a first direction; and second slits penetrating the plurality of memory regions, the second slits being arranged to be spaced apart from each other in a second direction intersecting the first direction. Gate lines included in each of the plurality of memory regions may be isolated from each other by the first slit. Each gate line located in the same layer among the gate lines included in each of the plurality of memory regions may extend through a first connection region between the second slits for each corresponding memory region.

Abstract: A semiconductor device may include a gate structure, a source structure that is disposed on the gate structure, channel structures that extend into the source structure through the gate structure and include a channel layer and a memory layer surrounding the channel layer, the memory layer including a cut area that exposes the channel layer, and a slit structure that extends into the source structure through the gate structure between the channel structures, an upper surface of the slit structure being disposed at a lower level than the cut area.

Abstract: The present disclosure relates to a data driving device and a display device including the same, and more particularly, to a data driving device and a display device including the same, capable of improving the slew rate and the display speed of the display device by overdriving a pixel of a display panel with a power voltage of the data driving device.

Abstract: The present disclosure, in an aspect, relates to a source driver to control a bias current, and more particularly, to a source driver, in which a bias current of a buffer is controlled depending on a distance between the source driver and a pixel in a data line and a position, regarding which a bias current is set, and the intensity of the bias current are changed in every frame so that unnecessary power consumption due to bias currents may be reduced and a block-dim phenomenon may be alleviated.

Abstract: A semiconductor device may include: a plurality of word lines; a select line; a channel layer extending into the select line through the word lines; a floating gate surrounding sidewalls of the channel layer between the channel layer and the select line; and a charge trap layer including a first and a second portion, wherein the first portion surrounds the sidewalls of the channel layer between the channel layer and the word lines and the second portion surrounds the floating gate between the channel layer and the select line.