Patents by Inventor Min Choi

Min Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240412989
    Abstract: Proposed are thermal processing apparatus, thermal processing method, and substrate treatment equipment, in which particle generation and damage to a substrate in the cooling process of the substrate can be prevented. The thermal processing apparatus includes a chamber having a processing zone therein, a plurality of chuck pins configured to support a substrate and move up or down individually, a heater configured to provide heat energy to the processing zone, a fluid supply port configured to supply a fluid to the processing zone, a fluid discharge port configured to discharge the fluid remaining in the processing zone to the outside, and a controller configured to control a treatment process of the substrate.
    Type: Application
    Filed: June 7, 2024
    Publication date: December 12, 2024
    Applicant: SEMES CO., LTD.
    Inventors: Young Eun JEON, Jong Won PARK, Sung Min CHOI, Woo Nam CHOI, Kun Hee KO, Yu Jung PARK, Jung Min SIM
  • Publication number: 20240414918
    Abstract: A semiconductor device may include: a gate structure including insulating layers and conductive layers alternately stacked; first supports located in the gate structure, each first support including a second channel layer; second supports located in the gate structure, each second support including a barrier layer; and contact structures extending between the second supports through the gate structure, wherein each contact structure is connected to a corresponding conductive layer.
    Type: Application
    Filed: September 8, 2023
    Publication date: December 12, 2024
    Inventors: Won Geun CHOI, Jung Shik JANG, Rho Gyu KWAK, Seok Min CHOI
  • Publication number: 20240410057
    Abstract: Proposed are a substrate processing method and a substrate processing apparatus. A substrate processing method according to an embodiment is for etching a thin film formed on a substrate at the atomic layer level, and includes a surface modification step of modifying a surface of the thin film by supplying a first gas including chlorine (Cl) to a processing space of a chamber in which the substrate is placed, a first purge step of removing the first gas remaining in the processing space by supplying a purge gas to the processing space, an etching step of etching the modified thin film by supplying a second gas including acetylacetone (Hacac) to the processing space, and a second purge step of removing the second gas remaining in the processing space by supplying the purge gas to the processing space.
    Type: Application
    Filed: March 25, 2024
    Publication date: December 12, 2024
    Applicants: SEMES CO., LTD., Research & Business Foundation SUNGKYUNKWAN UNIVERSITY
    Inventors: Sung Min CHOI, Heeyeop CHAE, Hojin KANG, Hyeongwu LEE, Heeju HA
  • Patent number: 12157082
    Abstract: The present disclosure relates to a removable filter system for removably coupling a filter unit to an air supply unit provided in a boiler. The filter unit is detachably coupled to the air supply unit, so that after removing the contaminated filter unit coupled to the air supply unit, a new filter unit can be coupled to the air supply unit or the existing filter unit can be reused after removing contaminants remaining in the filter.
    Type: Grant
    Filed: February 3, 2021
    Date of Patent: December 3, 2024
    Inventor: Jin Min Choi
  • Publication number: 20240395732
    Abstract: In a method of manufacturing a semiconductor device, an additional, induced-stress-limiting structure may be provided on a surface, which opposes stress that can be induced in a semiconductor device during its manufacturing processes. Such a stress compensation layer may be formed on a surface to compensate a stress applied to the rest of structure.
    Type: Application
    Filed: September 29, 2023
    Publication date: November 28, 2024
    Applicant: SK hynix Inc.
    Inventors: Seok Min CHOI, Jung Shik JANG, Rho Gyu KWAK, In Su PARK, Won Geun CHOI, Jung Dal CHOI
  • Publication number: 20240395324
    Abstract: A memory device includes: a memory cell array including a plurality of cell plugs; a first slit isolating the memory cell array into a plurality of memory regions, the first slit extending in a first direction; and second slits penetrating the plurality of memory regions, the second slits being arranged to be spaced apart from each other in a second direction intersecting the first direction. Gate lines included in each of the plurality of memory regions may be isolated from each other by the first slit. Each gate line located in the same layer among the gate lines included in each of the plurality of memory regions may extend through a first connection region between the second slits for each corresponding memory region.
    Type: Application
    Filed: November 7, 2023
    Publication date: November 28, 2024
    Applicant: SK hynix Inc.
    Inventors: Seok Min CHOI, Jung Shik JANG, Rho Gyu KWAK, Jeong Hwan KIM, In Su PARK, Won Geun CHOI, Jung Dal CHOI
  • Publication number: 20240397713
    Abstract: A semiconductor device may include a gate structure, a source structure that is disposed on the gate structure, channel structures that extend into the source structure through the gate structure and include a channel layer and a memory layer surrounding the channel layer, the memory layer including a cut area that exposes the channel layer, and a slit structure that extends into the source structure through the gate structure between the channel structures, an upper surface of the slit structure being disposed at a lower level than the cut area.
    Type: Application
    Filed: September 11, 2023
    Publication date: November 28, 2024
    Inventors: Rho Gyu KWAK, Jung Shik JANG, In Su PARK, Na Yeong YANG, Seok Min CHOI, Won Geun CHOI, Jung Dal CHOI
  • Patent number: 12154473
    Abstract: The present disclosure relates to a data driving device and a display device including the same, and more particularly, to a data driving device and a display device including the same, capable of improving the slew rate and the display speed of the display device by overdriving a pixel of a display panel with a power voltage of the data driving device.
    Type: Grant
    Filed: March 29, 2023
    Date of Patent: November 26, 2024
    Assignee: LX SEMICON CO., LTD.
    Inventor: Jung Min Choi
  • Patent number: 12154471
    Abstract: The present disclosure, in an aspect, relates to a source driver to control a bias current, and more particularly, to a source driver, in which a bias current of a buffer is controlled depending on a distance between the source driver and a pixel in a data line and a position, regarding which a bias current is set, and the intensity of the bias current are changed in every frame so that unnecessary power consumption due to bias currents may be reduced and a block-dim phenomenon may be alleviated.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: November 26, 2024
    Assignee: LX SEMICON CO., LTD.
    Inventors: Jung Min Choi, Hyung Sub Kim
  • Publication number: 20240388760
    Abstract: Disclosed is a display device including an IR receiving module configured to receive an IR signal including at least one of a control signal, a noise signal, and a modified signal from the outside, a filter module configured to output an output signal by filtering the modified signal at each filtering period, and a controller configured to obtain a period of the noise signal and set the filtering period based on the obtained period.
    Type: Application
    Filed: September 25, 2023
    Publication date: November 21, 2024
    Applicant: LG ELECTRONICS INC.
    Inventor: Hyun Min CHOI
  • Publication number: 20240389327
    Abstract: A semiconductor device may include: a plurality of word lines; a select line; a channel layer extending into the select line through the word lines; a floating gate surrounding sidewalls of the channel layer between the channel layer and the select line; and a charge trap layer including a first and a second portion, wherein the first portion surrounds the sidewalls of the channel layer between the channel layer and the word lines and the second portion surrounds the floating gate between the channel layer and the select line.
    Type: Application
    Filed: August 29, 2023
    Publication date: November 21, 2024
    Inventors: Seok Min CHOI, Jung Shik JANG
  • Patent number: 12148079
    Abstract: The present invention relates to a method and an apparatus for composing a background and a face by using a deep learning network, comprising: receiving an input of an original face image and a converted face image, and extracting data preprocessing and feature vectors for each image; generating a face feature vector mask from the extracted feature vectors; and generating a composite image by performing adaptive object normalization on the basis of the generated face feature vector mask.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: November 19, 2024
    Assignee: Klleon Inc.
    Inventors: Ji-Su Kang, Tae-Min Choi
  • Patent number: 12146083
    Abstract: The present disclosure relates to a surface protective film and a method for manufacturing an organic light emitting electronic device using the surface protective film.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: November 19, 2024
    Assignee: LG Chem, Ltd.
    Inventors: Jeong Min Choi, Hyun Cheol Kim, Sojin Kim, Hyungoo Kang, Jae Seung Lim
  • Publication number: 20240379622
    Abstract: A semiconductor package includes a base chip including a top surface extending in a first horizontal direction and a second horizontal direction intersecting the first horizontal direction, a semiconductor chip stack including a first semiconductor chip and a second semiconductor chip which are sequentially stacked on the base chip in a vertical direction and are aligned on respective sides in the vertical direction, first through vias penetrating the base chip and spaced apart from each other in the first horizontal direction, second through vias penetrating the first semiconductor chip and spaced apart from each other in the first horizontal direction, third through vias penetrating the second semiconductor chip and spaced apart from each other in the first horizontal direction, first connection pads contacting the first through vias, second connection pads contacting the second through vias, and third connection pads contacting the third through vias.
    Type: Application
    Filed: December 6, 2023
    Publication date: November 14, 2024
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung Yun WOO, Ji Min Choi, Joong Won Shin, Yeon Jin Lee, Jong Min Lee
  • Publication number: 20240376131
    Abstract: Proposed is an organometallic structure having excellent adsorption performance for volatile organic compounds (VOCs) and at the same time, having excellent outgassing prevention performance for adsorbed VOCs. An embodiment is a zirconium-based organometallic structure (MOF) characterized by simultaneously securing adsorption performance and outgassing prevention performance for VOCs by introducing an amine group (—NH2) into the crystal structure. An organometallic structure, which is a zirconium-based organometallic structure (MOF) containing fumaric acid as an organic linker, may have excellent adsorption performance and outgassing prevention performance for volatile organic compounds.
    Type: Application
    Filed: April 29, 2024
    Publication date: November 14, 2024
    Inventors: Kyung Min CHOI, Hyeon Shin LEE
  • Publication number: 20240371752
    Abstract: A semiconductor device may include: a first gate structure including a plurality of first conductive layers that are alternately stacked with a plurality of first insulating layers; a second gate structure including a plurality of second conductive layers that are alternately stacked with a plurality of second insulating layers; a third gate structure including third conductive layers that are alternately stacked with a plurality of third insulating layers; and a first contact plug extending into the first gate structure through the third gate structure and the second gate structure, the first contact plug connected to a first of the plurality of first conductive layers, and the first contact plug including a first inflection portion located at an interface between the second gate structure and the third gate structure.
    Type: Application
    Filed: April 8, 2024
    Publication date: November 7, 2024
    Applicant: SK hynix Inc.
    Inventors: Won Geun CHOI, Jung Shik JANG, Rho Gyu KWAK, Seok Min CHOI, Jeong Hwan KIM, Na Yeong YANG, In Su PARK, Jung Dal CHOI
  • Patent number: 12133545
    Abstract: The present application relates to a plant-soaked solution comprising sugars containing tagatose and to a method for producing same.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: November 5, 2024
    Assignee: CJ CHEILJEDANG CORPORATION
    Inventors: Su Jeong Kim, Jung Gyu Park, Youn Kyung Bak, Sung Bae Byun, Seung Won Park, Dong Chul Jung, Jong Min Choi
  • Patent number: 12132070
    Abstract: A display device includes conductive layers on a substrate, a via layer on the conductive layers, a first electrode and a second electrode extending in one direction on the via layer and spaced from each other, a first insulating layer on the first electrode and the second electrode, a plurality of light emitting elements on the first insulating layer, each of the light emitting elements having one end on the first electrode and an other end on the second electrode, and a first connection electrode and a second connection electrode on the first insulating layer, the first connection electrode overlapping the first electrode, and the second connection electrode overlapping the second electrode, wherein the first connection electrode and the second connection electrode are in contact with the conductive layers through contact portions.
    Type: Grant
    Filed: December 21, 2021
    Date of Patent: October 29, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jin Taek Kim, Ki Nyeng Kang, Jun Ho Bae, Jong Hwan Cha, Min Cheol Chae, Su Min Choi
  • Patent number: 12133410
    Abstract: A display device includes: a substrate including an opening area, a peripheral area surrounding the opening area, and a display area surrounding the peripheral area; a transistor disposed on the display area of the substrate; a first electrode electrically connected to the transistor; an intermediate layer overlapping the first electrode; a second electrode disposed on the intermediate layer; a first dam disposed on the peripheral area of the substrate; and a first encapsulation inorganic layer disposed on the second electrode, wherein the first encapsulation inorganic layer is in contact with a side of the first dam in the peripheral area.
    Type: Grant
    Filed: July 1, 2021
    Date of Patent: October 29, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Sang Yeol Kim, Eon Seok Oh, Woo Sik Jeon, Jung Min Choi
  • Publication number: 20240349503
    Abstract: There are provided a memory device and a manufacturing method of a memory device. The memory device includes a plurality of conductive layers, support structures penetrating the plurality of conductive layers, a contact hole exposing any one of the plurality of conductive layers and any one of the plurality of support structures, and a contact disposed in the contact hole.
    Type: Application
    Filed: September 25, 2023
    Publication date: October 17, 2024
    Applicant: SK hynix Inc.
    Inventors: Won Geun CHOI, Rho Gyu KWAK, Jung Shik JANG, Seok Min CHOI