Patents by Inventor Min Chul Shin

Min Chul Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220028687
    Abstract: Provided are a method of depositing a thin film and a method of manufacturing a semiconductor device using the same, and the method of depositing a thin film uses a substrate processing apparatus including a chamber, a substrate support on which a substrate is mounted, a gas supply unit, and a power supply unit that supplies high-frequency and low-frequency power to the chamber, and includes: a step of mounting, on the substrate support, the substrate including a lower thin film deposited under the condition of a process temperature in a low temperature range; a step of depositing an upper thin film on the lower thin film under the condition of the process temperature in the low temperature range; and a step of treating a surface of the upper thin film under the condition of the process temperature in the low temperature range.
    Type: Application
    Filed: June 28, 2021
    Publication date: January 27, 2022
    Applicant: WONIK IPS CO., LTD.
    Inventors: Su In KIM, Young Chul CHOI, Chang Hak SHIN, Min Woo PARK, Ji Hyun KIM, Kyung Mi KIM
  • Publication number: 20220028451
    Abstract: A nonvolatile memory apparatus includes a memory cell array and a memory control circuit. The memory cell array includes a plurality of sub arrays each including a plurality of memory cells coupled to a plurality of bit lines. The memory control circuit sequentially couples thereto, based on a single read command signal, at least a single bit line disposed on the respective sub arrays to sequentially access a memory cell coupled to the at least single bit line.
    Type: Application
    Filed: January 29, 2021
    Publication date: January 27, 2022
    Applicant: SK hynix Inc.
    Inventor: Min Chul SHIN
  • Patent number: 11152296
    Abstract: A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises a substrate having a first surface and a second surface opposite to the first surface, and comprising at least one first recess portion formed in a direction ranging from the first surface toward the second surface, a plurality of first recess conductive patterns formed in the first recess portion, and a first passive element inserted into the first recess portion of the substrate and having a first electrode and a second electrode electrically connected to the plurality of first recess conductive patterns.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: October 19, 2021
    Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD.
    Inventors: Jae Ung Lee, Yung Woo Lee, EunNaRa Cho, Dong Hyun Bang, Wook Choi, KooWoong Jeong, Byong Jin Kim, Min Chul Shin, Ho Jeong Lim, Ji Hyun Kim, Chang Hun Kim
  • Publication number: 20210134923
    Abstract: A display device includes a substrate which includes a display area and a non-display area, a transistor disposed in the display area, a pad disposed in the non-display area, and an insulating layer which is disposed on the transistor and defines an opening which overlaps the pad in a plan view. The pad includes a main layer, a first auxiliary layer on the main layer, and a second auxiliary layer on the first auxiliary layer, and the second auxiliary layer defines the opening.
    Type: Application
    Filed: June 29, 2020
    Publication date: May 6, 2021
    Inventors: Jee Hoon KIM, Shin Hyuk YANG, Jong Moo HUH, Dong Han KANG, Min Chul SHIN, Jun Ki LEE, Jae Seol CHO
  • Publication number: 20210104589
    Abstract: A display device a includes: a transistor disposed on a first substrate; an insulating layer disposed on the transistor; a first electrode disposed on the insulating layer; a partition disposed on the first electrode and the insulating layer, an opening is defined through the partition; a light-emitting element layer disposed in the opening; and a second electrode disposed on the light-emitting element layer and the partition. The insulating layer includes a first region and a third region having different heights from each other and a second region having an inclined surface connecting the first region and the third region, the first region has a lower height than the third region, and the first electrode overlaps the first region in a direction perpendicular to the first substrate.
    Type: Application
    Filed: July 30, 2020
    Publication date: April 8, 2021
    Inventor: Min Chul SHIN
  • Publication number: 20200355983
    Abstract: Methods and systems are described for adjusting an optical signal. An example device can comprise a plurality of waveguides. The device can comprise an interference structure optically coupled to the plurality of waveguides and configured to receive an optical signal and distribute the optical signal to the plurality of waveguides as a plurality of optical signals. The device can comprise a plurality of phase shifters coupled to corresponding waveguides of the plurality of waveguides and configured to adjust the phase of one or more of the plurality of optical signals. The device can comprise a plurality of emitters optically coupled to corresponding outputs of the plurality of phase shifters and configured to output the adjusted plurality of optical signals. The adjusted plurality of optical signals can be output as light patterns reconfigurable in at least one dimension.
    Type: Application
    Filed: May 11, 2020
    Publication date: November 12, 2020
    Inventors: Michal Lipson, Min Chul Shin, Aseema Mohanty, Kyle Watson
  • Patent number: 10831243
    Abstract: A flexible display device is provided. The flexible display device according to an embodiment of the present disclosure may include a first body, a second body, a first link, and a second link. According to an embodiment of the present disclosure, in an unfolding state, the first link and the second link may not protrude out of the first body and the second body, and the first link and the second link may be changed in a form that may protect the flexible display during folding.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: November 10, 2020
    Assignee: LG ELECTRONICS INC.
    Inventors: Hang Seok Kim, Gil Jae Lee, Min Chul Shin, Dong Jun Choi
  • Publication number: 20200326751
    Abstract: A flexible display device is provided. The flexible display device according to an embodiment of the present disclosure may include a first body, a second body, a first link, and a second link. According to an embodiment of the present disclosure, in an unfolding state, the first link and the second link may not protrude out of the first body and the second body, and the first link and the second link may be changed in a form that may protect the flexible display during folding.
    Type: Application
    Filed: December 5, 2019
    Publication date: October 15, 2020
    Applicant: LG ELECTRONICS INC.
    Inventors: Hang Seok KIM, Gil Jae LEE, Min Chul SHIN, Dong Jun CHOI
  • Patent number: 10747269
    Abstract: A flexible display device is provided. A flexible display device according to an embodiment of the present invention is configured to include a body, a moving plate, a flexible display, and a driving module. The driving module is configured to include a bracket, a sliding plate including a rack, a driving motor, and a driving gear. The driving module is coupled to a body and a moving plate after assembling the driving module so that it is possible to prevent a sliding plate which slidably moves together with a flexible display after assembling the flexible display device from being loosen and also prevent the idle operation of the driving gear.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: August 18, 2020
    Assignee: LG ELECTRONICS INC.
    Inventors: Dong Jun Choi, Hang Seok Kim, Min Chul Shin, Gil Jae Lee
  • Patent number: 10726915
    Abstract: A semiconductor memory apparatus includes a memory cell coupled between a bit line and a word line. A sensing line is disposed adjacent to the word line to form a capacitor together with the word line. A sense amplifier coupled to the sensing line generates an output signal by detecting a voltage level of the sensing line.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: July 28, 2020
    Assignee: SK hynix Inc.
    Inventor: Min Chul Shin
  • Publication number: 20200058351
    Abstract: A semiconductor memory apparatus includes a memory cell coupled between a bit line and a word line. A sensing line is disposed adjacent to the word line to form a capacitor together with the word line. A sense amplifier coupled to the sensing line generates an output signal by detecting a voltage level of the sensing line.
    Type: Application
    Filed: June 27, 2019
    Publication date: February 20, 2020
    Applicant: SK hynix Inc.
    Inventor: Min Chul SHIN
  • Patent number: 10528162
    Abstract: A display device integrated with a sensor includes a first substrate and a second substrate disposed while facing each other, and having exposed ends at different sides thereof, a sealing material configured to seal an overlapping region between the first and second substrates, a display unit including a plurality of pixels provided in a sealed region inside the sealing material, a sensor electrode unit formed on the second substrate, a first pad unit formed in an exposed part of the first substrate, and a second pad unit formed in an exposed part of the second substrate.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: January 7, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Bo-Kyung Choi, Jong-Moo Huh, Sung-Ho Kim, Min-Chul Shin
  • Patent number: 10497439
    Abstract: A memory apparatus may be provided. The memory apparatus may include a global bit line configured to receive a drift current. A voltage clamping circuit configured to limit a voltage level of the global bit line.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: December 3, 2019
    Assignee: SK hynix Inc.
    Inventors: Min Chul Shin, Ho Seok Em
  • Publication number: 20190348113
    Abstract: A memory apparatus may be provided. The memory apparatus may include a global bit line configured to receive a drift current. A voltage clamping circuit configured to limit a voltage level of the global bit line.
    Type: Application
    Filed: July 24, 2019
    Publication date: November 14, 2019
    Applicant: SK hynix Inc.
    Inventors: Min Chul SHIN, Ho Seok EM
  • Patent number: 10403356
    Abstract: A memory apparatus may be provided. The memory apparatus may include a global bit line configured to receive a drift current. A voltage clamping circuit configured to limit a voltage level of the global bit line.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: September 3, 2019
    Assignee: SK hynix Inc.
    Inventors: Min Chul Shin, Ho Seok Em
  • Publication number: 20190189205
    Abstract: A resistive memory apparatus includes a memory cell array, a local switch, and a global switch. The memory cell array may include a plurality of resistive memory cells coupled to a plurality of connection lines. The local switch may select a target connection line coupled to a target memory cell and a preset number of connection lines adjacent to the target connection line according to a signal obtained by decoding an address. The global switch may apply a preset level of voltage to the selected adjacent connection lines according to the signal obtained by decoding the address.
    Type: Application
    Filed: February 22, 2019
    Publication date: June 20, 2019
    Applicant: SK hynix Inc.
    Inventors: Jeong Ho YI, Min Chul SHIN
  • Publication number: 20180350734
    Abstract: A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises a substrate having a first surface and a second surface opposite to the first surface, and comprising at least one first recess portion formed in a direction ranging from the first surface toward the second surface, a plurality of first recess conductive patterns formed in the first recess portion, and a first passive element inserted into the first recess portion of the substrate and having a first electrode and a second electrode electrically connected to the plurality of first recess conductive patterns.
    Type: Application
    Filed: July 23, 2018
    Publication date: December 6, 2018
    Inventors: Jae Ung Lee, Yung Woo Lee, EunNaRa Cho, Dong Hyun Bang, Wook Choi, KooWoong Jeong, Byong Jin Kim, Min Chul Shin, Ho Jeong Lim, Ji Hyun Kim, Chang Hun Kim
  • Patent number: 10032705
    Abstract: A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises a substrate having a first surface and a second surface opposite to the first surface, and comprising at least one first recess portion formed in a direction ranging from the first surface toward the second surface, a plurality of first recess conductive patterns formed in the first recess portion, and a first passive element inserted into the first recess portion of the substrate and having a first electrode and a second electrode electrically connected to the plurality of first recess conductive patterns.
    Type: Grant
    Filed: May 8, 2016
    Date of Patent: July 24, 2018
    Assignee: Amkor Technology, Inc.
    Inventors: Jae Ung Lee, Yung Woo Lee, EunNaRa Cho, Dong Hyun Bang, Wook Choi, KooWoong Jeong, Byong Jin Kim, Min Chul Shin, Ho Jeong Lim, Ji Hyun Kim, Chang Hun Kim
  • Patent number: 10020263
    Abstract: Provided are a semiconductor package and a manufacturing method thereof for securing a space for mounting a semiconductor device by etching a temporary metal plate to form a plurality of conductive posts.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: July 10, 2018
    Assignee: AMKOR TECHNOLOGY, INC.
    Inventors: Kyoung Yeon Lee, Tae Yong Lee, Min Chul Shin, Se Man Oh
  • Publication number: 20180158524
    Abstract: A memory apparatus may be provided. The memory apparatus may include a global bit line configured to receive a drift current. A voltage clamping circuit configured to limit a voltage level of the global bit line.
    Type: Application
    Filed: November 16, 2017
    Publication date: June 7, 2018
    Applicant: SK hynix Inc.
    Inventors: Min Chul SHIN, Ho Seok EM