Patents by Inventor Min CHUNG

Min CHUNG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250134414
    Abstract: A computerized method is provided for detecting whether a subject is experiencing an event (e.g., an eating event or a scratching event). The method may comprise receiving time-series data derived from data recorded by an actigraphy device worn on a wrist of the subject and computing a set of birth and death coordinates for each topological feature of a plurality of topological features in the received time-series data. The method may further comprise calculating a digital feature based on the computed set of birth and death coordinates and determining whether the subject is experiencing the event based on the calculated digital feature. In some embodiments, methods are also provided for using Bayesian methods for selecting digital features to use in detecting whether the subject is experiencing the event.
    Type: Application
    Filed: January 30, 2023
    Publication date: May 1, 2025
    Inventors: Yu-Min CHUNG, Ju JI, Amir NIKOOIE, Bo ZHANG
  • Patent number: 12267993
    Abstract: The present disclosure provides a method of forming a semiconductor structure. The method includes providing a substrate including an isolation region, an active region adjacent to the isolation region, and a first top surface, wherein the isolation region includes an isolation trench filled with a dielectric material, and the active region includes a gate trench filled with a gate electrode material; forming a hard mask on the substrate; and performing an etching process to partially remove portions of the dielectric material and gate electrode material exposed by the hard mask to form a second top surface of the dielectric material and a third top surface of the gate electrode material, wherein the second top surface and the third top surface are substantially at the same level and are substantially lower than the first top surface.
    Type: Grant
    Filed: June 30, 2023
    Date of Patent: April 1, 2025
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Min-Chung Cheng
  • Publication number: 20250084381
    Abstract: The present invention relates to artificial skin using fibroblasts and keratinocytes, and more particularly, to a manufacturing device of artificial skin using cells differentiated from induced pluripotent stem cells (iPSCs).
    Type: Application
    Filed: June 29, 2023
    Publication date: March 13, 2025
    Applicant: CLECELL, CO. LTD.
    Inventors: Hyung Min Chung, C-Yoon Kim, Seul-Gi Lee, Gujin Chung
  • Publication number: 20250080323
    Abstract: A mouse device includes a detection function to detect non-human mouse events through encryption and a detection method thereof. A mouse retrieves variable characters, executes an encryption process on a plaintext mouse event to obtain a ciphertext mouse event based on the variable characters and fixed characters. A computer device executes a decryption process on the ciphertext mouse event to obtain the plaintext mouse event when receiving the ciphertext mouse event, executes the plaintext mouse event, and executes an interfering process when the mouse event is different or cannot be decrypted.
    Type: Application
    Filed: December 19, 2022
    Publication date: March 6, 2025
    Applicant: Voyetra Turtle Beach, Inc.
    Inventors: Thaddaeus Erasmus Georg Richard TETZNER, Chih Wei HUNG, Min Chung KE, Chih Kai YANG, Jhe Fu LIOU
  • Publication number: 20250076999
    Abstract: The present invention provides a mouse device with a detection function of non-human mouse events and a detection method thereof. A driver receives a plurality of movement mouse events through a computer device from a mouse device, executes a non-human movement detection on the movement mouse events to determine each movement mouse event as a suspicious event or a human-made event, executes an interference process when the suspicious events meet a non-human critical condition, and executes the plurality of movement mouse events when the suspicious events do not meet the non-human critical condition. The present invention can effectively detect non-human movement mouse events, and execute interference on the non-human movement mouse events to deter non-human operations.
    Type: Application
    Filed: December 19, 2022
    Publication date: March 6, 2025
    Applicant: Voyetra Turtle Beach, Inc.
    Inventors: Thaddaeus Erasmus Georg Richard TETZNER, Chih Wei HUNG, Min Chung KE, Chih Kai YANG, Jhe Fu LIOU
  • Patent number: 12245416
    Abstract: The present disclosure provides a method of forming a semiconductor structure. The method comprises providing a substrate comprising an isolation region, an active region adjacent to the isolation region, and a first top surface, wherein the isolation region includes an isolation trench filled with a dielectric material, and the active region includes a gate trench filled with a gate electrode material; forming a hard mask on the substrate; and performing an etching process to partially remove portions of the dielectric material and gate electrode material exposed by the hard mask to form a second top surface of the dielectric material and a third top surface of the gate electrode material, wherein the second top surface and the third top surface are substantially at the same level and are substantially lower than the first top surface.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: March 4, 2025
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Min-Chung Cheng
  • Publication number: 20250065716
    Abstract: In an embodiment, an apparatus for controlling a display of a vehicle includes a case device provided to cover one region of an interior ceiling of the vehicle, a display device interposed between the case device and the interior ceiling and including a display region to display at least one image, when one end portion of the case device is in an open position, and a controller configured to control the display device to display the at least one image by using the display region of the display device.
    Type: Application
    Filed: November 17, 2023
    Publication date: February 27, 2025
    Inventors: Chang Jin Ji, Soong Min Chung, Young Hyun Jeong, Dae Jin An
  • Publication number: 20250011729
    Abstract: The present invention relates to artificial skin using fibroblasts and keratinocytes, and more particularly, to a manufacturing method of artificial skin using cells differentiated from induced pluripotent stem cells (iPSCs). To this end, there is provided a manufacturing method of artificial skin using cells differentiated from iPSCs including the steps of: preparing induced pluripotent stem cells (iPSCs) of a donor (S100); performing differentiating fibroblasts from the iPSCs (S140) and differentiating keratinocytes from the iPSCs (S120) simultaneously or sequentially; injecting the fibroblasts and the keratinocytes using a 3D printer (S160); and manufacturing artificial skin by co-culturing the injected fibroblasts and keratinocytes (S160).
    Type: Application
    Filed: June 29, 2023
    Publication date: January 9, 2025
    Applicant: CLECELL, CO. LTD.
    Inventors: Hyung Min Chung, C-Yoon Kim, Seul-Gi Lee, Gujin Chung
  • Patent number: 12189761
    Abstract: Disclosed is a hooking detection method and system that may specify position information of a function referenced by an executable module from an outside or provided to the outside or a unique value of an executable code, and may determine application programming interface (API) hooking based on a classification acquired by comparing unique values or by clustering the unique values.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: January 7, 2025
    Assignee: LINE PLUS CORPORATION
    Inventors: Sang Min Chung, Joontae Choi, SangHun Jeon
  • Publication number: 20240413006
    Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes: forming a dummy via in a trench of a stacking structure with a bottom anti-reflection coated material, in which the stacking structure includes a low-k material layer and a cap layer, and the trench runs through the low-k material layer and the cap layer; and removing a portion of the dummy via by performing a first etching process and a second etching process, and in which the first etching process and the second etching process are performed such that a top surface of the dummy via is lower than a top surface of the low-k material layer and higher than a bottom surface of the low-k material layer.
    Type: Application
    Filed: August 20, 2024
    Publication date: December 12, 2024
    Inventor: Min-Chung CHENG
  • Publication number: 20240371686
    Abstract: A method of manufacturing a semiconductor structure is provided by embodiments of this disclosure, and the method includes the following steps. An insulating area and an active area are formed in a substrate. A first word line trench is formed in the active are. A first dielectric layer is deposited in the first word line trench and on the active area and the insulating area. A second word line trench is formed through etching the first dielectric layer. Besides, the second word line trench is linear and extends through the insulating area and the active area of the substrate, and a portion of the first dielectric layer is remained in a bottom of the second word line trench. Then, a word line structure is formed in the second word line trench. Moreover, a semiconductor structure is provided in this disclosure.
    Type: Application
    Filed: May 2, 2023
    Publication date: November 7, 2024
    Inventor: Min-Chung CHENG
  • Patent number: 12100615
    Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes: filling a trench of a stacking structure with a bottom anti-reflection coated material to form a dummy via in the trench, in which the stacking structure includes a low-k material layer and a cap layer, and the trench runs through the low-k material layer and the cap layer; and etching the dummy via by performing a first etching process and a second etching process.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: September 24, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Min-Chung Cheng
  • Publication number: 20240257910
    Abstract: A method, performed by an electronic device, of predicting gene expression from a histology image by using an artificial intelligence model may include identifying a first patch of the histology image divided into a plurality of patches, initial feature data of the first patch, and initial feature data of a second patch of the histology image, extracting global feature data of the first patch based on the initial feature data of the first patch and the initial feature data of the second patch, by using a first artificial intelligence model, extracting local feature data of the first patch from the first patch by using a second artificial intelligence model, and predicting a gene expression value for the first patch based on the global feature data of the first patch and the local feature data of the first patch, by using a third artificial intelligence model.
    Type: Application
    Filed: January 29, 2024
    Publication date: August 1, 2024
    Applicant: RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
    Inventors: Young Min CHUNG, Kyeong Chan IM, Joo Sang LEE
  • Patent number: 11963345
    Abstract: The present disclosure provides a semiconductor structure having a fin structure. The semiconductor includes a substrate defined with an active region. A first gate structure is disposed in the active region and includes a dielectric material. A second gate structure is disposed in the active region and includes the dielectric material. A fin structure having a first top surface is arranged to alternate with the first gate structure and the second gate structure. The first gate structure has a second top surface and the second gate structure has a third top surface. The second top surface and the third top surface are lower than the first top surface.
    Type: Grant
    Filed: March 24, 2023
    Date of Patent: April 16, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Min-Chung Cheng
  • Patent number: 11953366
    Abstract: A fluid level measurement system using a buoyant body includes a guide part installed in a direction perpendicular to the bottom surface of a fluid storage tank, and provided with a space in which a fluid can move therein; a buoyant body inserted into the guide part, and configured to float along the surface of the fluid inside the guide part; and a measurement part coupled to the top end of the guide part, and configured to measure the level of the surface of the fluid inside the fluid storage tank by transmitting a signal toward the buoyant body in the inner space of the guide part and then receiving a signal reflected from the buoyant body.
    Type: Grant
    Filed: July 7, 2022
    Date of Patent: April 9, 2024
    Assignee: HANRA IMS CO., LTD
    Inventors: Suk Joon Ji, Young Gu Kim, Jong Min Chung, Chae Ho Lee, I-Hwan Cheon, Kwang Ik Chun, Dong Sik Jang
  • Patent number: 11921874
    Abstract: A file protection method of a computer apparatus including a processor, the method including extracting classes from an executable file of a package file, classifying the classes into class groups, adding a loading code to a first class group among the class groups, the loading code configured to cause sequential loading of the class groups to a memory in a random loading order in response to execution of the package file, adding an integrity code to a second class group among the class groups, the integrity code configured to verify an integrity of a corresponding class group among the class groups or a previous class group among the class groups, the previous class group including the loading code configured to cause the corresponding class group to load, and regenerating the package file using the class groups after the adding the loading code and the adding the integrity code.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: March 5, 2024
    Assignee: LINE Plus Corporation
    Inventors: Sang Min Chung, Seol hwa Han, SangHun Jeon
  • Publication number: 20240057347
    Abstract: A memory element includes a substrate, a first electrode formed on the substrate, a phase-change heterolayer formed on the first electrode and electrically connected to the first electrode, and a second electrode formed on the phase-change heterolayer, wherein the phase-change heterolayer includes one or more confinement material layers and one or more phase-change material layers, and the confinement material layer includes a metal chalcogenide film.
    Type: Application
    Filed: July 7, 2023
    Publication date: February 15, 2024
    Applicants: Samsung Electronics Co., Ltd., UIF (University Industry Foundation), Yonsei University
    Inventors: Wooyoung YANG, Hyungjun Kim, Hajun Sung, Kiyeon Yang, Changseung Lee, Changyup Park, Seung-min Chung, Sangyoon Lee, Inkyu Sohn
  • Publication number: 20240047352
    Abstract: The present application provides a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a substrate and a wiring structure. The wiring structure includes at least one metal interconnect disposed on the substrate, at least one conductive feature disposed on the metal interconnect, and at least one diffusing barrier liner surrounding the conductive feature. The conductive feature has a head portion and a neck portion sandwiched between the metal interconnect and the head portion. The neck portion can have a first critical dimension, which gradually decreases at positions of increasing distance from the head portion.
    Type: Application
    Filed: July 7, 2023
    Publication date: February 8, 2024
    Inventor: MIN-CHUNG CHENG
  • Publication number: 20240047354
    Abstract: The present application provides a wiring structure, a semiconductor device having the wiring structure, and a method of manufacturing the semiconductor device. The wiring structure includes a substrate, a metallic layer above the substrate, at least one first conductive feature and at least one second conductive feature. The first and second conductive features are disposed between the substrate and the metallic layer; the first conductive feature has a first critical dimension, and the second conductive feature has a second critical dimension less than the first critical dimension. An effective resistance of the wiring structure can be adjusted by changing the critical dimensions of the first and second conductive features. The semiconductor device including the wiring structure and a method of manufacturing the semiconductor device are also provided.
    Type: Application
    Filed: August 3, 2022
    Publication date: February 8, 2024
    Inventor: MIN-CHUNG CHENG
  • Publication number: 20240047350
    Abstract: The present application provides a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a substrate and a wiring structure. The wiring structure includes at least one metal interconnect disposed on the substrate, at least one conductive feature disposed on the metal interconnect, and at least one diffusing barrier liner surrounding the conductive feature. The conductive feature has a head portion and a neck portion sandwiched between the metal interconnect and the head portion. The neck portion can have a first critical dimension, which gradually decreases at positions of increasing distance from the head portion.
    Type: Application
    Filed: August 3, 2022
    Publication date: February 8, 2024
    Inventor: MIN-CHUNG CHENG