Abstract: A testing apparatus has first and second IOs, first and second comparators, a data combining module, and first and second data output circuits. The first and second comparators respectively receive first and second test data. The data combining module electrically connected to the first and second comparators receive compared first and second test data of the first and second comparators, and further receive a command code. The first and second data output circuits are respectively connected to the first and second IOs, and are further electrically connected to the data combining module. According to the command code, the data combining module outputs the compared first and second test data respectively to the first and second IOs through the first and second data output circuits, or respectively to the second and first IOs through the second and first data output circuits.

Abstract: A testing apparatus has first and second IOs, first and second comparators, a data combining module, and first and second data output circuits. The first and second comparators respectively receive first and second test data. The data combining module electrically connected to the first and second comparators receive compared first and second test data of the first and second comparators, and further receive a command code. The first and second data output circuits are respectively connected to the first and second IOs, and are further electrically connected to the data combining module. According to the command code, the data combining module outputs the compared first and second test data respectively to the first and second IOs through the first and second data output circuits, or respectively to the second and first IOs through the second and first data output circuits.

Abstract: Embodiments of the invention relate to a reference voltage pre-processing circuit and method for a reference voltage buffer. The embodiments include a filter to control/reduce the noise and/or interference attached to a reference voltage to be provided to a reference voltage buffer by passing the reference voltage via two transistor in series. Furthermore, the embodiments include an auxiliary voltage circuit which interfaces the filter and the reference voltage buffer to avoid that the reference voltage buffer get an invalid reference voltage.

Abstract: In exemplary embodiments of the present disclosure, a level shifting circuit and an integrated circuit using the level shifting circuit are provided. Compared to the conventional level shifting circuit, the level shifting circuit herein further has another pair of PMOS transistors and another pair of NMOS transistors, wherein the other pair of the PMOS transistors is connected to the pair of the PMOS transistors, and the other pair of the NMOS transistors is connected to the pair of the NMOS transistors. PMOS and NMOS transistors of the level shifting circuit are protected, the lifetime of the level shifting circuit is increased, and the damage probability of the level shifting circuit is decreased. The other pair of the PMOS transistors being turned on can be operated in the saturation region rather than in the linear region, such that the operation speed of the level shifting circuit is enhanced.

Abstract: A control circuit applied in an e-fuse system selectively operates in a feeding mode and a reading mode. When the control circuit operates in the feeding mode, the control circuit is arranged to store a program code for indicating whether to connect a fuse of the e-fuse system thereto; and when the control circuit operates in the reading mode, the control circuit is arranged to read a state of the fuse of the e-fuse system coupled to the control circuit.

Abstract: An exemplary embodiment of the present disclosure illustrates a memory test system comprising a memory device, a probe card, and a tester. The memory device comprises a memory die with a plurality of memory banks, a plurality of input circuits, and a plurality of output circuits, wherein each of the input circuits has a first input pin and a second pin, the first input pins of the input circuits are used to read a plurality of patches of data stored in memory cells of the memory banks, and the second input pins are used to receive a compressed result. The output circuits receive compressed signals output from the input circuits, and the probe card mixes the compressed output signals output from the output circuits to output a mixed compressed output signal to the tester.

Abstract: An input buffer includes a first driving circuit, a second driving circuit, a pull up circuit, and a pull down circuit. The first driving circuit is arranged for driving a first input signal to generate an output signal. The second driving circuit is arranged for driving the output signal. The pull up circuit is arranged for selectively controlling the second driving circuit to pull up the output signal according to the first input signal and a second input signal. The pull down circuit is arranged for selectively controlling the second driving circuit to pull down the output signal according to the first input signal and the second input signal.

Abstract: An exemplary embodiment of the present disclosure illustrates a memory test system comprising a memory device, a probe card, and a tester. The memory device comprises a memory die with a plurality of memory banks, a plurality of input circuits, and a plurality of output circuits, wherein each of the input circuits has a first input pin and a second pin, the first input pins of the input circuits are used to read a plurality of patches of data stored in memory cells of the memory banks, and the second input pins are used to receive a compressed result. The output circuits receive compressed signals output from the input circuits, and the probe card mixes the compressed output signals output from the output circuits to output a mixed compressed output signal to the tester.

Abstract: An input buffer includes a first driving circuit, a second driving circuit, a pull up circuit, and a pull down circuit. The first driving circuit is arranged for driving a first input signal to generate an output signal. The second driving circuit is arranged for driving the output signal. The pull up circuit is arranged for selectively controlling the second driving circuit to pull up the output signal according to the first input signal and a second input signal. The pull down circuit is arranged for selectively controlling the second driving circuit to pull down the output signal according to the first input signal and the second input signal.

Abstract: An adaptive equalizer and operating method thereof are disclosed. The adaptive equalizer is oversampling-based. The adaptive equalizer includes a searching module, a compensation module, and an operating module. The searching module searches the equalizer setting from a lower compensation to a higher compensation to obtain a first equalizer setup value according a first monitored result of a monitor and then searches the equalizer setting from a higher compensation to a lower compensation to obtain a second equalizer setup value according to a second monitored result of the monitor. The operating module performs an operation on the first equalizer setup value and the second equalizer setup value to obtain an optimized equalizer setup value.

Abstract: A dynamic random-access memory (DRAM) and a method for testing the DRAM are provided. The DRAM includes a memory cell, a bit line associated with the memory cell, a local buffer, and a bit line sense amplifier (BLSA). The local buffer receives a first power voltage as power supply. The local buffer provides a ground voltage to the bit line when a data signal is de-asserted and provides the first power voltage to the bit line when the data signal is asserted. The BLSA receives a second power voltage as power supply. The BLSA provides the second power voltage to the bit line when the data signal and a wafer level burn-in test signal are both asserted. The second power voltage may be higher than the first power voltage. The wafer level burn-in test signal is asserted when the DRAM is in a wafer level burn-in test mode.

Abstract: A main word line driving circuit for driving word lines in a memory device comprises first and second level shifting units and an inverting unit. The first level shifting unit is configured to convert a decode signal into a first operative signal, and the second level shifting unit is configured to convert the decode signal into a second operative signal. The inverting unit is configured to receive the first and second operative signals. A supply voltage of the first level shifting unit is selectively switched to a first bias voltage when the plurality of word lines are selected or partially selected and switched the output voltage to a second bias voltage when the plurality of word lines are deselected.

Abstract: A multifunctional output driver capable of transmitting signals of different interfaces in different modes is provided, in which first and second current sources are provided, and first to fourth switching devices are coupled between the first and second current sources, and the first and second current source and the first to the fourth switching devices act as a current steering circuit. In a first transmission mode, the first and second switching devices are turned off, and the third and fourth switching devices and the first current source act as a current mode logic circuit to provide an output signal compatible with a first transmission interface according to an input signal from a pre-driver. In a second transmission mode, the current steering circuit outputs an output signal compatible with a second transmission interface according to the input signal from the pre-driver.

Abstract: The invention provides a delay lock loop circuit (DLL) for generating a locked signal, the DLL circuit includes: a phase detector, a first and a second voltage controlled delay chains, a charge pump and a duty cycle detection pump. The phase detector generates a phase detecting result by detecting a phase difference between the clock signal and the locked signal. The first and the second voltage controlled delay chains generate a first and a second delayed signals by delaying the clock signal according to the first and the second control signals, respectively. The charge pump is used for generating the first and the second control signal according to the phase detecting result. The duty cycle detection pump is used for controlling a voltage level of the second control signal according to the first and the second delayed signals.

Abstract: The invention provides a delay lock loop circuit (DLL) for generating a locked signal, the DLL circuit includes: a phase detector, a first and a second voltage controlled delay chains, a charge pump and a duty cycle detection pump. The phase detector generates a phase detecting result by detecting a phase difference between the clock signal and the locked signal. The first and the second voltage controlled delay chains generate a first and a second delayed signals by delaying the clock signal according to the first and the second control signals, respectively. The charge pump is used for generating the first and the second control signal according to the phase detecting result. The duty cycle detection pump is used for controlling a voltage level of the second control signal according to the first and the second delayed signals.

Abstract: A dynamic random-access memory (DRAM) and a method for testing the DRAM are provided. The DRAM includes a memory cell, a bit line associated with the memory cell, a local buffer, and a bit line sense amplifier (BLSA). The local buffer receives a first power voltage as power supply. The local buffer provides a ground voltage to the bit line when a data signal is de-asserted and provides the first power voltage to the bit line when the data signal is asserted. The BLSA receives a second power voltage as power supply. The BLSA provides the second power voltage to the bit line when the data signal and a wafer level burn-in test signal are both asserted. The second power voltage may be higher than the first power voltage. The wafer level burn-in test signal is asserted when the DRAM is in a wafer level burn-in test mode.

Abstract: An adaptive equalizer and operating method thereof are disclosed. The adaptive equalizer is oversampling-based. The adaptive equalizer includes a searching module, a compensation module, and an operating module. The searching module searches the equalizer setting from a lower compensation to a higher compensation to obtain a first equalizer setup value according a first monitored result of a monitor and then searches the equalizer setting from a higher compensation to a lower compensation to obtain a second equalizer setup value according to a second monitored result of the monitor. The operating module performs an operation on the first equalizer setup value and the second equalizer setup value to obtain an optimized equalizer setup value.

Abstract: The invention provides a test circuit for n input/output arrays. Each of the n input/output arrays has M pairs of input/output. The test circuit includes M write drivers and M comparing circuits. The ith write driver provides an ith test signal to the ith inputs of all of the n input/output arrays, and 1?i?M. The jth comparing circuit determines if jth output signals of all of the n input/output arrays are the same, and outputs a jth comparing result correspondingly, and 1?j?M. The invention also provides a method of testing n input/output arrays. The invention also provides a storage device.

Abstract: A delay-locked loop (DLL) and a method of using the DLL are provided. The DLL receives an external clock signal and outputs an internal clock signal. The DLL includes a variable delay line and a phase detector. The variable delay line delays the external clock signal and outputs a delayed external clock signal. The phase detector compares the phase of the external clock signal and the phase of the internal clock signal. The method includes the following steps: providing the delayed external clock signal directly to the phase detector of the DLL as the internal clock signal in a high frequency mode; and inverting the delayed external clock signal and providing an inverted delayed external clock signal to the phase detector as the internal clock signal in a low frequency mode.

Abstract: A dynamic RAM which includes a first inverter, a second inverter, a sense amplifier, a first pair of switches, a pair of bit lines, and a dynamic RAM cell. The first inverter receives a first driving signal. A power end of the first inverter is coupled to a first voltage source. The second inverter receives a second driving signal output from the first inverter. A power end of the second inverter is coupled to a second voltage source. The sense amplifier senses and amplifies a voltage difference between a first sensing signal and a second sensing signal. A power end of the sense amplifier is coupled to a third voltage source, wherein a voltage value of the second voltage source is between a voltage value of the first voltage source and a voltage value of the third voltage source.