Abstract: A voltage regulator in a semiconductor memory has: a comparing unit including first and second bias current sources, for comparing an output voltage with first and second reference voltages under control of a first signal, the second bias current source being ON under control of a second signal; and a driver active element, coupled to the comparing unit, for outputting the output voltage. Before sensing operations, the output voltage is reset to the second reference voltage. During the sensing operations, the output voltage is maintained at the first reference voltage and the second signal is asserted for turning ON the second bias current source for raising speed of the comparing unit. After the sensing operations, the output voltage is reset to the second reference voltage.

Abstract: A multifunctional output driver capable of transmitting signals of different interfaces in different modes is provided, in which first and second current sources are provided, and first to fourth switching devices are coupled between the first and second current sources, and the first and second current source and the first to the fourth switching devices act as a current steering circuit. In a first transmission mode, the first and second switching devices are turned off, and the third and fourth switching devices and the first current source act as a current mode logic circuit to provide an output signal compatible with a first transmission interface according to an input signal from a pre-driver. In a second transmission mode, the current steering circuit outputs an output signal compatible with a second transmission interface according to the input signal from the pre-driver.

Abstract: A delay circuit has: an inverting receiver with a resistive element, the inverting receiver having an input node for receiving an input signal and an output node coupled to the resistive element; a capacitive element, coupled to the output node of the inverting receiver and the resistive element; a first transistor, having lower turned ON voltage at higher temperature; a second transistor, used for generating a rail to rail signals on a terminal of the first transistor; and an output inverter, having an input node coupled to the first transistor and an output node for outputting an output signal of the delay circuit. Further, a third transistor is used for enhancing pulling low of the output signal of the delay circuit.

Abstract: A voltage regulator in a semiconductor memory has: a comparing unit including first and second bias current sources, for comparing an output voltage with first and second reference voltages under control of a first signal, the second bias current source being ON under control of a second signal; and a driver active element, coupled to the comparing unit, for outputting the output voltage. Before sensing operations, the output voltage is reset to the second reference voltage. During the sensing operations, the output voltage is maintained at the first reference voltage and the second signal is asserted for turning ON the second bias current source for raising speed of the comparing unit. After the sensing operations, the output voltage is reset to the second reference voltage.

Abstract: A voltage regulator as a stable power supply to internal circuits in a semiconductor memory device is provided. This regulator includes a comparing unit, a first driver transistor, a feedback unit, an auxiliary control unit, a first switch, a second switch, and a second driver transistor. The comparing unit compares a reference voltage with a feedback signal to control the first driver transistor and maintain the internal power supply at a stable level. The second driver transistor, controlled by the first and second switches responsive to a trigger signal corresponding abrupt current consumptions and the auxiliary control unit responsive to the comparing result, supplies sufficient and appropriate current to the internal circuits and prevents the internal power supply from excessive overshoot and drop-out.

Abstract: A phase locked loop (PLL) with phase rotation spreading includes a phase detector, a charge pump, a filter, a voltage controlled oscillator (VCO) and a selector. The phase detector receives a reference clock signal and a feedback clock signal to thereby produce an error signal. The charge pump converts the error signal into a current signal. The filter converts the current signal into a voltage signal. The VCO produces N clock signals with a same frequency in accordance with the voltage signal, where the N clock signals have phases ?0 to ?N?1 respectively, and ?j indicates a lead of over ?j+1, for j=0, 1, . . . , N?2. The selector selects one from the N clock signals in accordance with a predetermined sequence to thereby produce a target clock signal, and finely adjusts a frequency of the target clock signal for a spreading operation.

Abstract: A voltage regulator as a stable power supply to internal circuits in a semiconductor memory device is provided. This regulator includes a comparing unit, a first driver transistor, a feedback unit, an auxiliary control unit, a first switch, a second switch, and a second driver transistor. The comparing unit compares a reference voltage with a feedback signal to control the first driver transistor and maintain the internal power supply at a stable level. The second driver transistor, controlled by the first and second switches responsive to a trigger signal corresponding abrupt current consumptions and the auxiliary control unit responsive to the comparing result, supplies sufficient and appropriate current to the internal circuits and prevents the internal power supply from excessive overshoot and drop-out.

Abstract: A LVDS (Low Voltage Differential Signal) driver with a high PSRR (Power Supply Rejection Ration) includes a first current source for providing a working current, a switch unit for receiving the working current and determining the current directions of an output current at first and second signal nodes according to first and second input signals, a second current source connected between the switch unit and a low working power voltage, a common mode feedback unit for generating a common mode control signal according to voltages on the first and second signal nodes of the switch unit, a common mode resistance unit connected in parallel with the second current source and having a resistance value controlled by the common mode control signal, and a compensation unit connected in parallel with the second current source for compensating the current variation of the first current source caused by power noise.

Abstract: An adaptive equalizer apparatus with digital eye-opening monitor unit and the method thereof are provided. The apparatus comprises an equalizer unit, a sampling unit, and an eye-opening monitor unit. The equalizer unit equalizes a first signal to a second signal. The sampling unit over-samples the second signal and determines the logic status of the second signal according to the sampling data. The eye-opening monitor unit processes the sampling data and outputs a detecting signal according to the processing result. The detecting signal represents the adequacy of the parameters of the equalizer unit, and the equalizer unit determines whether to change its parameters according to the detecting signal.

Abstract: A clock frequency divider circuit and method of dividing a clock frequency are provided. The clock frequency divider circuit includes a first flip-flop circuit, a second flip-flop circuit, a third flip-flop circuit, a first logic control unit and a second logic control unit, wherein the first flip-flop circuit has two clock input terminals connected to the second and third flip-flop circuits respectively and two control signal input terminals connected to the first and second logic control units respectively. The second and third flip-flop circuits count rising edges and falling edges of an input frequency under control of the first and second flip-flop circuits and accordingly, symmetric output signals are output from the first flip-flop circuit.

Abstract: A transmitter circuit, a receiver circuit and an interface switching module for SATA or SAS interface are provided. The invention uses transistors as elements with different impedance and also provides impedance modulating method in coordination with the exterior circuit and the layout design so as to develop an auto-switching mechanism between SATA and SAS interfaces, thereby integrating two transmission interfaces in a single system.

Abstract: A clock frequency divider circuit and method of dividing a clock frequency are provided. The clock frequency divider circuit includes a first flip-flop circuit, a second flip-flop circuit, a third flip-flop circuit, a first logic control unit and a second logic control unit, wherein the first flip-flop circuit has two clock input terminals connected to the second and third flip-flop circuits respectively and two control signal input terminals connected to the first and second logic control units respectively. The second and third flip-flop circuits count rising edges and falling edges of an input frequency under control of the first and second flip-flop circuits and accordingly, symmetric output signals are output from the first flip-flop circuit.

Abstract: A memory device and a method for burn in test are characterized by a plurality of sub-array word line leak-current limited units and a plurality of single word line leak-current limited units. They are used to limit the current in each word line to a predetermined word line current value. In burn-in test mode, the output of a word line driver is kept in a high impedance state. The bit line stress voltage is applied to the row of memory cells through a normal read-write path. A voltage generator for generating a substantially stable voltage is also provided. In burn-in test mode, the even word lines and the odd word lines are grouped separately and the word line stress voltage is applied to the even word lines and to the odd word lines alternately.

Abstract: A memory device and a method for burn-in test. The memory device has a plurality of sub-array word line leak-current limited units and a plurality of single word line leak-current limited units. They are used to limit the current in each word line to a predetermined word line current value. In burn-in test mode, the output of a word line driver is kept in a high impedance state. The bit line stress voltage is applied to the row of memory cells through a normal read-write path. A voltage generator for generating a substantially stable voltage is also provided. In burn-in test mode, the even word lines and the odd word lines are grouped separately and the word line stress voltage is applied to the even word lines and to the odd word lines alternately.

Abstract: A LVDS (Low Voltage Differential Signal) driver with a high PSRR (Power Supply Rejection Ration) includes a first current source for providing a working current, a switch unit for receiving the working current and determining the current directions of an output current at first and second signal nodes according to first and second input signals, a second current source connected between the switch unit and a low working power voltage, a common mode feedback unit for generating a common mode control signal according to voltages on the first and second signal nodes of the switch unit, a common mode resistance unit connected in parallel with the second current source and having a resistance value controlled by the common mode control signal, and a compensation unit connected in parallel with the second current source for compensating the current variation of the first current source caused by power noise.

Abstract: A memory device and a method for burn-in test are described. The memory device has a plurality of sub-array word line leak-current limited units and a plurality of single word line leak-current limited units. They are used to limit the current in each word line to a predetermined word line current value. In burn-in test mode, the output of a word line driver is kept in a high impedance state. The bit line stress voltage is applied to the row of memory cells through a normal read-write path. A voltage generator for generating a substantially stable voltage is also provided. In burn-in test mode, the even word lines and the odd word lines are grouped separately and the word line stress voltage is applied to the even word lines and to the odd word lines alternately.

Abstract: A memory device and a method for burn-in test are described. The memory device has a plurality of sub-array word line leak-current limited units and a plurality of single word line leak-current limited units. They are used to limit the current in each word line to a predetermined word line current value. In burn-in test mode, the output of a word line driver is kept in a high impedance state. The bit line stress voltage is applied to the row of memory cells through a normal read-write path. A voltage generator for generating a substantially stable voltage is also provided. In burn-in test mode, the even word lines and the odd word lines are grouped separately and the word line stress voltage is applied to the even word lines and to the odd word lines alternately.

Abstract: A high-speed laser driver for signal noise on the electrical analysis point. The driver includes a power supply, for providing a test voltage in the system; a pulse generator, for providing a test frequency in a noise testing of the system; a regulable test IC with different signal pads capable of regulable testing signal noise with the test frequency from the pulse generator and the test voltage from the power supply in a plurality of built-in specific structures, under the basis of an assigned current standard; and a digital detection device with a display, for displaying and recording the result of the regulable test.

Abstract: A high-speed laser driver for signal noise on the electrical analysis point. The driver includes a power supply, for providing a test voltage in the system; a pulse generator, for providing a test frequency in a noise testing of the system; a regulable test IC with different signal pads capable of regulable testing signal noise with the test frequency from the pulse generator and the test voltage from the power supply in a plurality of built-in specific structures, under the basis of an assigned current standard; and a digital detection device with a display, for displaying and recording the result of the regulable test.

Abstract: A boost circuit for driving word lines in a memory device, comprises: a delaying module for delaying signal to turn on a refresh cycle of the boost circuit; a precharge timing controlling module for controlling the timing of the refresh cycle, wherein the delay module transmitting the signal to the precharge timing controlling module for disabling and enabling the precharge timing controlling module; a precharge module for supplying charge to a first capacitor and a second capacitor, wherein the precharge module is controlled by the precharge timing controlling module; a first capacitor connected to the precharge module and charge the word lines for storing charges; when the precharge module stops to charge the first capacitor, the first capacitor starts to charge the word lines in 2k refresh mode and charge both of the word lines and the second capacitor in 4k refresh mode of the memory device; a second capacitor connected to the precharge module and charge the word lines for storing charges, wherein the sec