Patents by Inventor Min Fu

Min Fu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170111454
    Abstract: A method and system for transmitting and receiving data packets between two network nodes via one or more end-to-end connections. An interface is provided for selecting one or more possible end-to-end connection(s) or established end-to-end connection(s). The method and system may further comprise receiving a policy, wherein one or more selected end-to-end connections are established based, at least in part, on the policy. The policy may also restrict or promote selection of certain established end-to-end connection(s) via the interface provided. The selected and established end-to-end connection(s) are used for transmitting and receiving data packets.
    Type: Application
    Filed: March 28, 2013
    Publication date: April 20, 2017
    Inventors: Patrick Ho Wai SUNG, Ho Ming CHAN, Kit Wai CHAU, Min-Fu TSAI
  • Patent number: 9612479
    Abstract: The present invention provides a pixel structure disposed on a substrate, and the pixel structure includes an alignment layer, a common electrode, and a pixel electrode. The alignment layer is disposed on the substrate, and the alignment layer has a first section and a second section. The first section has a first alignment direction, and the second section has a second alignment direction perpendicular to the first alignment direction. The common electrode is disposed between the substrate and the alignment layer, and the pixel electrode is disposed between the substrate and the alignment layer.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: April 4, 2017
    Assignee: Chunghwa Picture Tubes, Ltd.
    Inventors: Hung-Yu Wu, Hsin-Min Fu, Jan-Tian Lian
  • Patent number: 9582633
    Abstract: Among other things, techniques and systems for 3D modeling of a FinFET device and for detecting a variation for a design layout based upon a 3D FinFET model are provided. For example, a fin height of a FinFET device is determined based upon imagery of the FinFET device. The fin height and a 2D FinFET model for the FinFET device are used to create a 3D FinFET model. The 3D FinFET model takes into account the fin height, which is evaluated to identify fin height variations amongst FinFET devices within the design layout. For example, a fin height variation is determined based upon a proximity pattern density, a fin pitch, a gate length, or other parameters/measurements. A voltage threshold variation is determined based upon the fin height variation. This allows the design layout to be modified to decrease the variation.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: February 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chung-min Fu, Meng-Fu You, Po-Hsiang Huang, Wen-Hao Cheng
  • Patent number: 9484552
    Abstract: A flexible device substrate includes a flexible substrate, a device layer, and a waterproof layer. The flexible substrate has a top surface and a bottom surface disposed opposite to each other. The device layer is disposed on the top surface of the flexible substrate. The waterproof layer is disposed on the bottom surface of the flexible substrate.
    Type: Grant
    Filed: April 23, 2014
    Date of Patent: November 1, 2016
    Assignee: Chunghwa Picture Tubes, Ltd.
    Inventors: Hsin-Min Fu, Jan-Tian Lian, Chia-Sheng Hsieh, Hung-Yu Wu, Tzu-Yu Ting
  • Publication number: 20160286001
    Abstract: A method and system for processing Domain name Services (DNS) request in a gateway with at least one local area network (LAN) interface and at least one wide area network (WAN) interface. The gateway receives a first DNS request from a first host via one of the at least one LAN interface of the gateway. The gateway then selects a plurality of DNS servers. At least one of the plurality of DNS server is accessible through at least one tunnel. The gateway transmits a plurality of new DNS requests to the plurality of DNS servers. The contents of the plurality of new DNS requests are the same as the content of the first DNS request.
    Type: Application
    Filed: April 22, 2014
    Publication date: September 29, 2016
    Applicant: PISMO LABS TECHNOLOGY LIMITED
    Inventors: Alex Wing Hong Chan, Ho Ming Chan, Kit Wai Chau, Chi Pan Yip, Min-Fu Tsai
  • Publication number: 20160273942
    Abstract: A time grating linear displacement sensor based on an alternating light field, comprising a fixed pole plate and a movable pole plate, wherein the upper part and the lower part of the fixed pole plate are respectively provided with a row of square fixed pole plate light-transmitting surfaces which are uniformly distributed; the upper part and the lower part at the rear of the fixed pole plate are respectively provided with one group of light-emitting devices; the upper part and the lower part of the movable pole plate are respectively provided with two semi-sinusoidal movable pole plate light-transmitting surfaces; and four light-sensitive receiving units are fixed on the movable pole plate, the photoelectric receiving surfaces of the light-sensitive receiving units covering the movable pole plate light-transmitting surfaces. The two groups of light-emitting devices respectively provide an alternating light field. The movable pole plate moves relative to the fixed pole plate.
    Type: Application
    Filed: November 13, 2014
    Publication date: September 22, 2016
    Inventors: Donglin Peng, Xiaokang Liu, Min Fu, Haojie Xia, Ge Zhu
  • Publication number: 20160269353
    Abstract: A method and system for processing Domain name Services (DNS) request in a gateway. The gateway receives a DNS request from a host from its local area network. The gateway then selects DNS server(s) and transmits a new DNS request to at least one DNS server(s). DNS server(s) may or may not be accessible through a first tunnel. The contents of the new DNS request are the same as the content of the received DNS request. Further, when the gateway receives a DNS response corresponding to the DNS request, it determines a decision whether to transfer data to the host whose IP address is specified in the DNS response through a second tunnel. The decision may be based on a geographical location of an IP address.
    Type: Application
    Filed: April 22, 2014
    Publication date: September 15, 2016
    Applicant: PISMO LABS TECHNOLOGY LIMITED
    Inventors: Alex Wing Hong Chan, Ho Ming Chan, Kit Wai Chau, Chi Pan Yip, Min-Fu Tsai
  • Patent number: 9412692
    Abstract: A flexible microsystem structure is provided. The flexible microsystem structure includes a flexible substrate; and a chip disposed over the flexible substrate, wherein the chip is bonded to the flexible substrate by a plurality of bonding elements disposed over the flexible substrate; wherein the flexible substrate has at least one trench disposed under the chip and disposed along at least one side of at least one of the bonding elements.
    Type: Grant
    Filed: January 13, 2015
    Date of Patent: August 9, 2016
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Yu-Ting Cheng, Yu-Min Fu
  • Publication number: 20160204051
    Abstract: A flexible microsystem structure is provided. The flexible microsystem structure includes a flexible substrate; and a chip disposed over the flexible substrate, wherein the chip is bonded to the flexible substrate by a plurality of bonding elements disposed over the flexible substrate; wherein the flexible substrate has at least one trench disposed under the chip and disposed along at least one side of at least one of the bonding elements.
    Type: Application
    Filed: January 13, 2015
    Publication date: July 14, 2016
    Inventors: Yu-Ting CHENG, Yu-Min FU
  • Patent number: 9367655
    Abstract: The present disclosure provides a method. The method includes obtaining an integrated circuit (IC) layout. The method includes providing a polishing process simulation model. The method includes performing a lithography pattern check (LPC) process to the IC layout. The LPC process is performed at least in part using the polishing process simulation model. The method includes detecting, in response to the LPC process, possible problem areas on the IC layout. The method includes modifying the polishing process simulation model. The method includes repeating the performing the LPC process and the detecting the possible problem areas using the modified polishing process simulation model.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: June 14, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: I-Chang Shih, Chung-min Fu, Ying-Chou Cheng, Yung-Fong Lu, Feng-Yuan Chiu, Chiu Hsiu Chen
  • Patent number: 9355250
    Abstract: The present embodiments provide a method and system for rapidly scanning a file, wherein the method includes obtaining a data packet, the data packet comprising secure file characteristic information for determining whether a file in a system is a secure file, and scanning file characteristic information of files in the system one by one, if the currently scanned file characteristic information matches secure file characteristic information in the data packet identifying a file as a secure file, skipping an anti-virus scanning for the current file, and continuing to scan a next file. By using the data packet, when a new user performs a first scanning, a file with identical characteristic information as that in the data packet can be skipped, which can reduce the time for the first scanning.
    Type: Grant
    Filed: February 5, 2013
    Date of Patent: May 31, 2016
    Assignee: Beijing Qihoo Technology Company Limited
    Inventors: Guiqiang Zou, Min Fu
  • Patent number: 9324178
    Abstract: A system comprises an electron beam directed toward a three-dimensional object with one tilting angle and at least two azimuth angles, a detector configured to receive a plurality of scanning electron microscope (SEM) images from the three-dimensional object and a processor configured to calculate a height and a sidewall edge of the three-dimensional object.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: April 26, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Hao Cheng, Chih-Chiang Tu, Chung-Min Fu, Ajay Nandoriya
  • Patent number: 9318504
    Abstract: One or more techniques or systems for mitigating density gradients between two or more regions of cells are provided herein. In some embodiments, an array of cells is associated with a dummy region. For example, the array of cells includes an array of gates and an array of OD regions. In some embodiments, the array of gates includes a first set of gates associated with a first gate dimension and a second set of gates associated with a second gate dimension. In some embodiments, the array of OD regions includes a first set of OD regions associated with a first OD dimension and a second set of OD regions associated with a second OD dimension. In this manner, at least one of a pattern density, gate density, or OD density is customized to a region associated with active cells, thus mitigating density gradients between respective regions.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: April 19, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Yu-Jung Chang, C. R. Hsu, Chin-Chang Hsu, Wen-Ju Yang, Chung-min Fu
  • Patent number: 9311440
    Abstract: A method includes identifying at least one local power segment of a circuit, estimating at least one performance parameter of the at least one power segment based on a computer-based simulation of the circuit, and changing a design of the circuit based on at least one electromigration avoidance strategy if the at least one parameter is greater than or equal to a threshold value. A data file representing the circuit is stored if the at least one parameter is less than the threshold value.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: April 12, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jerry Kao, King-Ho Tam, Meng-Xiang Lee, Li-Chung Hsu, Chi-Yeh Yu, Chung-Min Fu, Chung-Hsing Wang
  • Publication number: 20160091761
    Abstract: The present invention provides a pixel structure disposed on a substrate, and the pixel structure includes an alignment layer, a common electrode, and a pixel electrode. The alignment layer is disposed on the substrate, and the alignment layer has a first section and a second section. The first section has a first alignment direction, and the second section has a second alignment direction perpendicular to the first alignment direction. The common electrode is disposed between the substrate and the alignment layer, and the pixel electrode is disposed between the substrate and the alignment layer.
    Type: Application
    Filed: December 2, 2015
    Publication date: March 31, 2016
    Inventors: Hung-Yu Wu, Hsin-Min Fu, Jan-Tian Lian
  • Patent number: 9262568
    Abstract: Embodiments of the present invention are a system, a computer program product, and a method for implementing an integrated circuit design. The method for implementing an integrated circuit design includes accessing an original electronic representation of an integrated circuit layout from a first user file, and accessing a defined sensitivity index that characterizes an impact of the dummy pattern on the functional component. The impact of the dummy pattern on the functional component is analyzed and it is determined whether the impact is within a limit of the sensitivity index. One of a plurality of features of the dummy pattern is adjusted if the impact is not within the limit to form a generated electronic representation of a modified integrated circuit layout, and the generated electronic representation is output to a second user file. The integrated circuit layout includes a dummy pattern and a functional component.
    Type: Grant
    Filed: April 20, 2010
    Date of Patent: February 16, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Min Fu, Meng-Fu You
  • Patent number: 9245073
    Abstract: In some embodiments, in a method, a layout of a circuit is received. A netlist with indicated pattern density (PD)-dependent mismatch elements associated with different PDs, respectively, is generated using the layout. A simulation on the netlist is performed such that when the PD-dependent mismatch elements are modeled in the simulation, corresponding model parameters of the PD-dependent mismatch elements are generated using variation distributions with different spreads.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: January 26, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chung-Min Fu, Wan-Yu Lo, Shih-Cheng Yang, Chung-Kai Lin, Yung-Chow Peng
  • Publication number: 20160020222
    Abstract: One or more techniques or systems for mitigating density gradients between two or more regions of cells are provided herein. In some embodiments, an array of cells is associated with a dummy region. For example, the array of cells includes an array of gates and an array of OD regions. In some embodiments, the array of gates includes a first set of gates associated with a first gate dimension and a second set of gates associated with a second gate dimension. In some embodiments, the array of OD regions includes a first set of OD regions associated with a first OD dimension and a second set of OD regions associated with a second OD dimension. In this manner, at least one of a pattern density, gate density, or OD density is customized to a region associated with active cells, thus mitigating density gradients between respective regions.
    Type: Application
    Filed: September 28, 2015
    Publication date: January 21, 2016
    Inventors: Yu-Jung Chang, C.R. Hsu, Chin-Chang Hsu, Wen-Ju Yang, Chung-min Fu
  • Publication number: 20160014144
    Abstract: Disclosed is a method for multiple antivirus engines to clear viruses in parallel. The multiple antivirus engines include at least one first antivirus engine and at least one second antivirus engine. The method for multiple antivirus engines to clear viruses in parallel includes: invoking a first antivirus engine, and scanning a first classified file in a file to be checked for and rid of viruses to obtain a first scanning result which includes a target file in the first classified file (101); invoking a second antivirus engine, and scanning other file except the target file in the first classified file in the file to be checked for and rid of viruses to obtain a second scanning result (102); and outputting the first scanning result and the second scanning result (103). Also disclosed are a device for multiple antivirus engines to clear viruses in parallel, a method for processing a computer virus, and a device for processing a computer virus.
    Type: Application
    Filed: September 21, 2015
    Publication date: January 14, 2016
    Inventors: Chongyang XIE, Min FU, Guiqiang ZOU
  • Patent number: 9223919
    Abstract: A computer implemented method comprises accessing a 3D-IC model stored in a tangible, non-transitory machine readable medium, processing the model in a computer processor to generate a temperature map containing temperatures at a plurality of points of the 3D-IC under the operating condition; identifying an electromigration (EM) rating factor, and calculating and outputting from the processor data representing a temperature-dependent EM current constraint at each point.
    Type: Grant
    Filed: December 10, 2013
    Date of Patent: December 29, 2015
    Assignee: Taiwan Semiconductor Manufacturing, Co., Ltd.
    Inventors: Chi-Yeh Yu, Chung-Min Fu, Ping-Heng Yeh