Abstract: A received layout identifies a plurality of circuit components to be included in an integrated circuit (IC) layer for double patterning the layer using two photomasks, the layout including a plurality of first patterns to be included in the first photomask and at least one second pattern to be included in the second photomask. A selected one of the first patterns has first and second endpoints, to be replaced by a replacement pattern connecting the first endpoint to a third endpoint. At least one respective keep-out region is provided adjacent to each respective remaining first pattern except for the selected first pattern. Data are generated representing the replacement pattern, such that no part of the replacement pattern is formed in any of the keep-out regions. Data representing the remaining first patterns and the replacement pattern are output.

Abstract: A system comprises an electron beam directed toward a three-dimensional object with one tilting angle and at least two azimuth angles, a detector configured to receive a plurality of scanning electron microscope (SEM) images from the three-dimensional object and a processor configured to calculate a height and a sidewall edge of the three-dimensional object.

Abstract: Among other things, techniques and systems for 3D modeling of a FinFET device and for detecting a variation for a design layout based upon a 3D FinFET model are provided. For example, a fin height of a FinFET device is determined based upon imagery of the FinFET device. The fin height and a 2D FinFET model for the FinFET device are used to create a 3D FinFET model. The 3D FinFET model takes into account the fin height, which is evaluated to identify fin height variations amongst FinFET devices within the design layout. For example, a fin height variation is determined based upon a proximity pattern density, a fin pitch, a gate length, or other parameters/measurements. A voltage threshold variation is determined based upon the fin height variation. This allows the design layout to be modified to decrease the variation.

Abstract: Disclosed is a method for multiple antivirus engines to clear viruses in parallel. The multiple antivirus engines include at least one first antivirus engine and at least one second antivirus engine. The method for multiple antivirus engines to clear viruses in parallel includes: invoking a first antivirus engine, and scanning a first classified file in a file to be checked for and rid of viruses to obtain a first scanning result which includes a target file in the first classified file (101); invoking a second antivirus engine, and scanning other file except the target file in the first classified file in the file to be checked for and rid of viruses to obtain a second scanning result (102); and outputting the first scanning result and the second scanning result (103). Also disclosed are a device for multiple antivirus engines to clear viruses in parallel, a method for processing a computer virus, and a device for processing a computer virus.

Abstract: This disclosure provides a method and system for rapidly scanning a file, which relates to the field of network technologies. The method of the application comprises: obtaining a data packet, the data packet comprising secure file characteristic information for determining whether a file in a system is a secure file; and scanning file characteristic information of files in the system one by one, if the currently scanned file characteristic information matches secure file characteristic information in the data packet identifying a file as a secure file, skipping an anti-virus scanning for the current file, and continuing to scan a next file.

Abstract: Methods and systems for processing Domain Name Service (DNS) request in a gateway with a plurality of WAN network interfaces. After receiving a first DNS request via one of network interfaces of the gateway, the gateway selects at least one DNS server and at least one access network and then transmits a plurality of new DNS requests to the selected at least one DNS server through the selected at least one access network and via one of network interfaces of the gateway.

Abstract: A method comprises directing an electron beam toward a sidewall of a three-dimensional region of a semiconductor device with a tilting angle and a first azimuth angle, detecting a first projection distance of the sidewall through a detector placed over the semiconductor device, directing the electron beam toward the sidewall with the tilting angle and a second azimuth angle, detecting a second projection distance of the sidewall, calculating a height of the three-dimensional region using a first function, wherein the first function includes the first tilting angle, the first azimuth angle, the second azimuth angle and the projection distance of the sidewall and calculating a sidewall edge of the three-dimensional region using a second function, wherein the second function includes the first azimuth angle, the second azimuth angle and the projection distance of the sidewall.

Abstract: A method for manufacturing an alignment layer is provided. An alignment material having an ultraviolet reactive functional group is formed on a substrate. A pre-baking process is performed on the alignment material located on the substrate. An ultraviolet polarizer is provided on the substrate. An aligning process is performed on the pre-baked alignment material, so as to irradiate an ultraviolet light to the substrate. The ultraviolet light passes through the ultraviolet polarizer and irradiates to the pre-baked alignment material. A post-baking process is performed on the alignment material after being aligned, so as to fully cure the alignment material.

Abstract: An integrated circuit structure includes a plurality of power or ground rails for an integrated circuit, the plurality of power or ground rails vertically separated on a plane, a plurality of functional cells between the plurality of power rails or between the plurality of ground rails or both, and a jumper connection between the vertically separated power rails or ground rails, the jumper connection within a vertically aligned gap among the plurality of functional cells. A method of mitigating IR drop and electromigration affects in an integrated circuit includes forming a plurality of power rails or ground rails, each of the power rails or ground rails on separate vertical levels of a plane of an integrated circuit layout and connecting with a jumper connection at least two power rails or two ground rails, the jumper connection within a vertically aligned gap among cells of the integrated circuit.

Abstract: Apparatus includes a machine readable storage medium for storing a template library having at least one template. The template is to include a first layout representation of at least one pattern to be formed by multi-patterning a single layer of an IC. The pattern has a plurality of portions to be formed using a plurality of respectively different photomasks. The first layout representation includes data identifying on which photomask each portion is to be located. An electronic design automation (EDA) tool includes a processor configured to receive a hardware description language representation of at least a part of a circuit and generate a second layout representation of the part of the circuit having a plurality of polygons. The EDA tool has a matching module that identifies and outputs an indication of whether one or more of the plurality of portions matches a subset of the plurality of polygons.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a workpiece and a plurality of first conductive lines disposed over the workpiece in a metallization layer. A plurality of second conductive lines is disposed over the workpiece in the metallization layer. The plurality of second conductive lines comprises a greater vertical height in a cross-sectional view of the workpiece than a vertical height of the plurality of first conductive lines.

Abstract: A method includes retrieving a first component information of a secured portion of a package, wherein the first component information is encrypted. The step of retrieving includes decrypting the first component information. A thermal resistance-network (R-network) is generated from the decrypted first component information. A temperature map of the package is generated using the thermal R-network and a second component information of an unsecured portion of the package, wherein the secured portion and the unsecured portion are bonded to each other.

Abstract: A stator structure includes a main body having multiple frames each having an arc panel, a main tooth, at least one secondary tooth, at least one main coil and at least one secondary coil. The main tooth and the secondary tooth are disposed at one face of the arc panel. The main coil is installed at the main tooth, and the secondary coil is installed at the secondary coil. A rotor is penetrated through the stator structure. The frames are in a multi-layer circular arrangement at the rotor, and a dislocation angle exists between the frame at any layer and the frame at the neighboring layer.

Abstract: A method for manufacturing an alignment layer is provided. An alignment material having an ultraviolet reactive functional group is formed on a substrate. A pre-baking process is performed on the alignment material located on the substrate. An ultraviolet polarizer is provided on the substrate. An aligning process is performed on the pre-baked alignment material, so as to irradiate an ultraviolet light to the substrate. The ultraviolet light passes through the ultraviolet polarizer and irradiates to the pre-baked alignment material. A post-baking process is performed on the alignment material after being aligned, so as to fully cure the alignment material.

Abstract: A current vector controlled synchronous reluctance motor and control method thereof, wherein the motor has a coil on each of the teeth. The coils form a U-phase winding, a V-phase winding and a W-phase winding. The phase windings receive a balanced three-phase current vector to induce closed magnetic field lines, such that the coils induce same magnetic poles adjacent to the rotor unit. Two short magnetic routes are formed along three adjacent teeth and the rotor unit. The efficiency of the reluctance motor is high.

Abstract: Apparatus includes a machine readable storage medium for storing a template library having at least one template. The template is to include a first layout representation of at least one pattern to be formed by multi-patterning a single layer of an IC. The pattern has a plurality of portions to be formed using a plurality of respectively different photomasks. The first layout representation includes data identifying on which photomask each portion is to be located. An electronic design automation (EDA) tool includes a processor configured to receive a hardware description language representation of at least a part of a circuit and generate a second layout representation of the part of the circuit having a plurality of polygons. The EDA tool has a matching module that identifies and outputs an indication of whether one or more of the plurality of portions matches a subset of the plurality of polygons.

Abstract: A utility includes a design-for-manufacturing (DFM) checker configured to check layout patterns of an integrated circuit, and a layout change instruction generator configured to generate a layout change instruction based on a result generated by the DFM checker. The DFM checker and the layout change instruction generator are embodied on a non-transitory storage media. The layout change instruction specifies an identifier of a layout pattern among the layout patterns, and a respective layout change to be performed on the layout pattern.

Abstract: A computer implemented method comprises accessing a 3D-IC model stored in a tangible, non-transitory machine readable medium, inputting a power profile in a computer processor, generating a transient temperature profile based on the 3D-IC model, identifying a potential thermal violation at a corresponding operating time interval and a corresponding location of a plurality of points of the 3D-IC design, and outputting data representing the potential thermal violation. The 3D-IC model represents a 3D-IC design comprising a plurality of elements in a stack configuration. The power profile is applied to the plurality of elements of the 3D-IC design as a function of an operating time. The transient temperature profile includes temperatures at a plurality of points of the 3D-IC design as a function of an operating time.

Abstract: A computer implemented method comprises accessing a 3D-IC model stored in a tangible, non-transitory machine readable medium, processing the model in a computer processor to generate a temperature map containing temperatures at a plurality of points of the 3D-IC under the operating condition; identifying an electromigration (EM) rating factor, and calculating and outputting from the processor data representing a temperature-dependent EM current constraint at each point.

Abstract: A computer implemented method comprises accessing a 3D-IC model stored in a tangible, non-transitory machine readable medium, inputting a power profile in a computer processor, generating a transient temperature profile based on the 3D-IC model, identifying a potential thermal violation at a corresponding operating time interval and a corresponding location of a plurality of points of the 3D-IC design, and outputting data representing the potential thermal violation. The 3D-IC model represents a 3D-IC design comprising a plurality of elements in a stack configuration. The power profile is applied to the plurality of elements of the 3D-IC design as a function of an operating time. The transient temperature profile includes temperatures at a plurality of points of the 3D-IC design as a function of an operating time.