Abstract: In some embodiments, in a method, a layout of a circuit is received. A netlist with indicated pattern density (PD)-dependent mismatch elements associated with different PDs, respectively, is generated using the layout. A simulation on the netlist is performed such that when the PD-dependent mismatch elements are modeled in the simulation, corresponding model parameters of the PD-dependent mismatch elements are generated using variation distributions with different spreads.

Abstract: One or more techniques or systems for mitigating density gradients between two or more regions of cells are provided herein. In some embodiments, an array of cells is associated with a dummy region. For example, the array of cells includes an array of gates and an array of OD regions. In some embodiments, the array of gates includes a first set of gates associated with a first gate dimension and a second set of gates associated with a second gate dimension. In some embodiments, the array of OD regions includes a first set of OD regions associated with a first OD dimension and a second set of OD regions associated with a second OD dimension. In this manner, at least one of a pattern density, gate density, or OD density is customized to a region associated with active cells, thus mitigating density gradients between respective regions.

Abstract: Disclosed is a method for multiple antivirus engines to clear viruses in parallel. The multiple antivirus engines include at least one first antivirus engine and at least one second antivirus engine. The method for multiple antivirus engines to clear viruses in parallel includes: invoking a first antivirus engine, and scanning a first classified file in a file to be checked for and rid of viruses to obtain a first scanning result which includes a target file in the first classified file (101); invoking a second antivirus engine, and scanning other file except the target file in the first classified file in the file to be checked for and rid of viruses to obtain a second scanning result (102); and outputting the first scanning result and the second scanning result (103). Also disclosed are a device for multiple antivirus engines to clear viruses in parallel, a method for processing a computer virus, and a device for processing a computer virus.

Abstract: A computer implemented method comprises accessing a 3D-IC model stored in a tangible, non-transitory machine readable medium, processing the model in a computer processor to generate a temperature map containing temperatures at a plurality of points of the 3D-IC under the operating condition; identifying an electromigration (EM) rating factor, and calculating and outputting from the processor data representing a temperature-dependent EM current constraint at each point.

Abstract: A current vector controlled synchronous reluctance motor and control method thereof, wherein the motor has a coil on each of the teeth. The coils form a U-phase winding, a V-phase winding and a W-phase winding. The phase windings receive a balanced three-phase current vector to induce closed magnetic field lines, such that the coils induce same magnetic poles adjacent to the rotor unit. Two short magnetic routes are formed along three adjacent teeth and the rotor unit. The efficiency of the reluctance motor is high.

Abstract: One or more techniques or systems for mitigating density gradients between two or more regions of cells are provided herein. In some embodiments, an array of cells is associated with a dummy region. For example, the array of cells includes an array of gates and an array of OD regions. In some embodiments, the array of gates includes a first set of gates associated with a first gate dimension and a second set of gates associated with a second gate dimension. In some embodiments, the array of OD regions includes a first set of OD regions associated with a first OD dimension and a second set of OD regions associated with a second OD dimension. In this manner, at least one of a pattern density, gate density, or OD density is customized to a region associated with active cells, thus mitigating density gradients between respective regions.

Abstract: A thread-based microfluidic guiding system is provided and includes a substrate, two fiber threads arranged on the substrate in a cross manner. The two fiber threads are used as physical guiding pathways to guide a sample fluid and a buffer fluid, respectively. The two fiber threads have capillary action, so that the sample fluid, the buffer fluid or a mixture fluid thereof can flow along fiber surfaces of the two fiber threads, which can be pre-treated by plasma. The thread-based microfluidic guiding system of the present invention is different from recessed microfluidic channel structures, and can simplify system structure, lower manufacture cost, accelerate detection operation and enhance detection sensitivity.

Abstract: A method includes providing a first layout of a semiconductor device comprising a plurality of cells representing circuit elements, and providing a cell library comprising a plurality of cells in a processor. The circuit elements comprise a plurality of fin field effect transistors (Fin-FETs). Each of the plurality of cells in the cell library is displayed with a respectively different marker indicating a respective fin height. The method further includes generating a second layout for the semiconductor device to be fabricated, by placing or replacing at least one cell from the cell library in a respective location in the first layout. The at least one cell from the cell library comprises a Fin-FET with a respective fin height different from an adjacent Fin-FET in the second layout.

Abstract: Apparatus includes a machine readable storage medium for storing a template library having at least one template. The template is to include a first layout representation of at least one pattern to be formed by multi-patterning a single layer of an IC. The pattern has a plurality of portions to be formed using a plurality of respectively different photomasks. The first layout representation includes data identifying on which photomask each portion is to be located. An electronic design automation (EDA) tool includes a processor configured to receive a hardware description language representation of at least a part of a circuit and generate a second layout representation of the part of the circuit having a plurality of polygons. The EDA tool has a matching module that identifies and outputs an indication of whether one or more of the plurality of portions matches a subset of the plurality of polygons.

Abstract: In some embodiments, in a method, a layout of a circuit is received. A netlist with indicated pattern density (PD)-dependent mismatch elements associated with different PDs, respectively, is generated using the layout. A simulation on the netlist is performed such that when the PD-dependent mismatch elements are modeled in the simulation, corresponding model parameters of the PD-dependent mismatch elements are generated using variation distributions with different spreads.

Abstract: A fabrication method of a layer structure for mounting a semiconductor device is provided, which includes the steps of: providing a base material, wherein the base material has a conductive layer having a first surface having a plurality of first conductive elements and an opposite second surface having a plurality of second conductive elements, and a first encapsulant formed on the first surface of the conductive layer for encapsulating the first conductive elements; partially removing the conductive layer to form a circuit layer that electrically connects the first conductive elements and the second conductive elements; and forming a second encapsulant on a bottom surface of the first encapsulant for encapsulating the circuit layer and the second conductive elements, thus reducing the fabrication difficulty and increasing the product yield.

Abstract: An oxide semiconductor composition comprises graphene, a metal oxide precursor, and a solvent. Based on a total weight of the oxide semiconductor composition, a concentration of the graphene is between 0.01 and 10 wt %, a concentration of the metal oxide is between 0.01 and 30 wt %, and a concentration of the solvent is between 60 and 99.98 wt %.

Abstract: A flexible device substrate includes a flexible substrate, a device layer, and a waterproof layer. The flexible substrate has a top surface and a bottom surface disposed opposite to each other. The device layer is disposed on the top surface of the flexible substrate. The waterproof layer is disposed on the bottom surface of the flexible substrate.

Abstract: A method of making a semiconductor device includes determining, by a processor, a first pattern density of a first region, determining a second pattern density of a second region, determining a pattern density gradient from the first region to the second region, determining whether the pattern density gradient exceeds a pattern density gradient threshold and performing a placement or a routing of the semiconductor device if the pattern density gradient is less than or equal to the pattern density gradient threshold.

Abstract: An oxide semiconductor composition comprises graphene, a metal oxide precursor, and a solvent. Based on a total weight of the oxide semiconductor composition, a concentration of the graphene is between 0.01 and 10 wt %, a concentration of the metal oxide is between 0.01 and 30 wt %, and a concentration of the solvent is between 60 and 99.98 wt %.

Abstract: A method includes providing a first layout of a semiconductor device comprising a plurality of cells representing circuit elements, and providing a cell library comprising a plurality of cells in a processor. The circuit elements comprise a plurality of fin field effect transistors (Fin-FETs). Each of the plurality of cells in the cell library is displayed with a respectively different marker indicating a respective fin height. The method further includes generating a second layout for the semiconductor device to be fabricated, by placing or replacing at least one cell from the cell library in a respective location in the first layout. The at least one cell from the cell library comprises a Fin-FET with a respective fin height different from an adjacent Fin-FET in the second layout.

Abstract: The present invention discloses a polarizing layer of a liquid crystal panel and manufacturing method thereof. A polarized ultraviolet (UV) light is irradiated on a UV reactive liquid crystal layer to form a polarized UV reactive liquid crystal layer having polarization properties, and it is used as the polarizing layer of the liquid crystal panel. The present invention has advantages of being thin in the thickness thereof, in addition to having high temperature resistance, as well as a simple manufacturing process, thereby reducing production costs.

Abstract: A method of making a semiconductor device includes arranging a first cell and a second cell, determining, by a processor, a first pattern density of a first cell, determining a second pattern density of a second cell, determining a pattern density gradient from the first pattern density to the second pattern density, determining whether the pattern density gradient exceeds a pattern density gradient threshold, and indicating a design change if the pattern density gradient exceeds than the pattern density gradient threshold.

Abstract: A method of making a semiconductor device includes arranging a first cell and a second cell, determining, by a processor, a first pattern density of a first cell, determining a second pattern density of a second cell, determining a pattern density gradient from the first pattern density to the second pattern density, determining whether the pattern density gradient exceeds a pattern density gradient threshold, and indicating a design change if the pattern density gradient exceeds than the pattern density gradient threshold.

Abstract: A received layout identifies a plurality of circuit components to be included in an integrated circuit (IC) layer for double patterning the layer using two photomasks, the layout including a plurality of first patterns to be included in the first photomask and at least one second pattern to be included in the second photomask. A selected one of the first patterns has first and second endpoints, to be replaced by a replacement pattern connecting the first endpoint to a third endpoint. At least one respective keep-out region is provided adjacent to each respective remaining first pattern except for the selected first pattern. Data are generated representing the replacement pattern, such that no part of the replacement pattern is formed in any of the keep-out regions. Data representing the remaining first patterns and the replacement pattern are output.