Patents by Inventor Min HAO

Min HAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9062841
    Abstract: A lighting system having neural hubs that connect to other neural hubs in a manner that allows a lighting system to be configured in a two dimensional pattern that can propagate out from a single neural hub. Straight sections can be provided for use in connection with the neural hubs to enhance the configurability of the lighting system.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: June 23, 2015
    Assignee: ABL IP Holding, LLC
    Inventors: Michael Trung Tran, Darren Blum, Peter Y. Y. Ngai, Min-Hao Michael Lu, Jeannine Fisher Wang, Aaron Mathew Engel-Hall
  • Patent number: 9052102
    Abstract: An electrical interconnect system is comprised of at least one and suitably a plurality of thin body light sources, such as OLED panels, to be electrified. The thin body light source or sources have a thin profile and include a back side provided with surface contact electrodes for energizing the thin body light sources, which can be relatively large area electrodes for providing a relatively large contact surface area. A connector circuit supported by a thin body support structure is provided for making desired electrical connections between thin body light sources or to a voltage or current source when the thin body support structure is brought into engagement with the thin body light sources.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: June 9, 2015
    Assignee: ABL IP Holding, LLC
    Inventors: Min-Hao Michael Lu, Michael Trung Tran
  • Patent number: 9041140
    Abstract: A device includes a semiconductor substrate having a front side and a backside, a photo-sensitive device disposed on the front side of the semiconductor substrate, and a first and a second grid line parallel to each other. The first and the second grid lines are on the backside of, and overlying, the semiconductor substrate. The device further includes an adhesion layer, a metal oxide layer over the adhesion layer, and a high-refractive index layer over the metal layer. The adhesion layer, the metal oxide layer, and the high-refractive index layer are substantially conformal, and extend on top surfaces and sidewalls of the first and the second grid lines.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: May 26, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiu-Ko JangJian, Min Hao Hong, Ting-Chun Wang, Chung-Ren Sun
  • Publication number: 20150132913
    Abstract: Embodiments that relate to mechanisms for providing a stable dislocation profile are provided. A semiconductor substrate having a gate stack is provided. An opening is formed adjacent to a side of the gate stack. A first part of an epitaxial growth structure is formed in the opening. A second part of the epitaxial growth structure is formed in the opening. The first part and the second part of the epitaxial growth structure are formed along different directions.
    Type: Application
    Filed: November 14, 2013
    Publication date: May 14, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Min-Hao HONG, Shiu-Ko JANGJIAN, Chih-Tsung LEE, Miao-Cheng LIAO
  • Patent number: 9006070
    Abstract: Methods of making an integrated circuit are disclosed. An embodiment method includes etching a trench in a silicon substrate, depositing a first layer of isolation material in the trench, the first layer of isolation material projecting above surface of the silicon substrate, capping the first layer of isolation material by depositing a second layer of isolation material, the second layer of isolation material extending along at least a portion of sidewalls of the first layer of isolation material, epitaxially-growing a silicon layer upon the silicon substrate, the silicon layer horizontally adjacent to the second layer of isolation material, and forming a gate structure on the silicon layer, the gate structure defining a channel.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: April 14, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min Hao Hong, You-Hua Chou, Chih-Tsung Lee, Shiu-Ko JangJian, Miao-Cheng Liao, Hsiang-Hsiang Ko, Chen-Ming Huang
  • Publication number: 20150041851
    Abstract: A method includes performing a first epitaxy to grow a first epitaxy layer of a first conductivity type, and performing a second epitaxy to grow a second epitaxy layer of a second conductivity type opposite the first conductivity type over the first epitaxy layer. The first and the second epitaxy layers form a diode. The method further includes forming a gate dielectric over the first epitaxy layer, forming a gate electrode over the gate dielectric, and implanting a top portion of the first epitaxy layer and the second epitaxy layer to form a source/drain region adjacent to the gate dielectric.
    Type: Application
    Filed: October 28, 2014
    Publication date: February 12, 2015
    Inventors: Shiu-Ko JangJian, Min Hao Hong, Kei-Wei Chen, Chi-Cherng Jeng
  • Patent number: 8889461
    Abstract: A method includes performing a first epitaxy to grow a first epitaxy layer of a first conductivity type, and performing a second epitaxy to grow a second epitaxy layer of a second conductivity type opposite the first conductivity type over the first epitaxy layer. The first and the second epitaxy layers form a diode. The method further includes forming a gate dielectric over the first epitaxy layer, forming a gate electrode over the gate dielectric, and implanting a top portion of the first epitaxy layer and the second epitaxy layer to form a source/drain region adjacent to the gate dielectric.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: November 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiu-Ko JangJian, Min Hao Hong, Kei-Wei Chen, Chih-Cherng Jeng
  • Publication number: 20140268766
    Abstract: A direct-indirect luminaire 11 is comprised of a support frame 23, 25 for supporting multiple planar light sources 15 that emit light from both their top and bottom planar surfaces 17, 19 for producing up-light and down-light in characteristic light distribution patterns. The planar light sources, which are preferably edge-fed light waveguides, can be supported in the support frame in different rotational orientations that can be changed to change the light distribution characteristics of the luminaire.
    Type: Application
    Filed: March 17, 2014
    Publication date: September 18, 2014
    Inventor: Min-Hao Michael Lu
  • Patent number: 8796105
    Abstract: A method for depositing a polysilazane on a semiconductor wafer is provided. The method includes steps of disposing a silazane onto the semiconductor wafer, and heating the silazane to form the polysilazane on the semiconductor wafer. An apparatus for preparing a polysilazane on a semiconductor wafer is also provided.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: August 5, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: You-Hua Chou, Chih-Tsung Lee, Min-Hao Hong, Ming-Huei Lien, Chih-Jen Wu, Chen-Ming Huang
  • Patent number: 8772899
    Abstract: Methods and apparatus for a backside illuminated (BSI) image sensor device are disclosed. A BSI sensor device is formed on a substrate comprising a photosensitive diode. The substrate may be thinned at the backside, then a B doped Epi-Si(Ge) layer may be formed on the backside surface of the substrate. Additional layers may be formed on the B doped Epi-Si(Ge) layer, such as a metal shield layer, a dielectric layer, a micro-lens, and a color filter.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: July 8, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiu-Ko JangJian, Min Hao Hong, Kei-Wei Chen, Ying-Lang Wang
  • Publication number: 20140179071
    Abstract: Methods of making an integrated circuit are disclosed. An embodiment method includes etching a trench in a silicon substrate, depositing a first layer of isolation material in the trench, the first layer of isolation material projecting above surface of the silicon substrate, capping the first layer of isolation material by depositing a second layer of isolation material, the second layer of isolation material extending along at least a portion of sidewalls of the first layer of isolation material, epitaxially-growing a silicon layer upon the silicon substrate, the silicon layer horizontally adjacent to the second layer of isolation material, and forming a gate structure on the silicon layer, the gate structure defining a channel.
    Type: Application
    Filed: February 25, 2014
    Publication date: June 26, 2014
    Inventors: Min Hao Hong, You-Hua Chou, Chih-Tsung Lee, Shiu-Ko JangJian, Miao-Cheng Liao, Hsiang-Hsiang Ko, Chen-Ming Huang
  • Publication number: 20140162534
    Abstract: A polishing system for polishing a semiconductor wafer includes a wafer support for holding the semiconductor wafer, and a first polishing pad for polishing a region of the semiconductor wafer. The semiconductor wafer has a first diameter, and the first polishing pad has a second diameter shorter than the first diameter.
    Type: Application
    Filed: December 6, 2012
    Publication date: June 12, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Chi LIN, Kun-Tai WU, You-Hua CHOU, Chih-Tsung LEE, Min Hao HONG, Chih-Jen WU, Chen-Ming HUANG, Soon-Kang HUANG, Chin-Hsiang CHANG, Chih-Yuan YANG
  • Publication number: 20140134685
    Abstract: The invention provides a recombinant cell having a nucleotide sequence encoding a polypeptide which is a lipase having at least 40% amino acid sequence identity to a polypeptide having SEQ ID NO:1, and methods of using the recombinant cell to produce triacylglycerols or to increase oil production by the cell.
    Type: Application
    Filed: November 7, 2013
    Publication date: May 15, 2014
    Applicant: Board of Trustees of Michigan State University
    Inventors: Christoph Benning, Xiaobo Li, Bensheng Liu, Min-Hao Kuo, Barbara Sears
  • Patent number: 8692299
    Abstract: An integrated circuit device and a process for making the integrated circuit device. The integrated circuit device including a substrate having a trench formed therein, a first layer of isolation material occupying the trench, a second layer of isolation material formed over the first layer of isolation material, an epitaxially-grown silicon layer on the substrate and horizontally adjacent the second layer of isolation material, and a gate structure formed on the epitaxially-grown silicon, the gate structure defining a channel.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: April 8, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min Hao Hong, You-Hua Chou, Chih-Tsung Lee, Shiu-Ko JangJian, Miao-Cheng Liao, Hsiang Hsiang Ko, Chen-Ming Huang
  • Patent number: 8687474
    Abstract: A recording apparatus characterized in that comprising a firmware configured to execute the following operation: performing a recording operation onto a rewritable optical recording medium with a recording speed selected from one of a plurality of recording speeds for an one-time optical recording medium; wherein the recording layer of the rewritable optical recording medium comprises at least four elements from Ge, In, Sb, Te, and Sn, wherein the component proportion of Sb/Te is ranged from 3 to 8, and the thickness of the recording layer is ranged from 3 nm to 25 nm.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: April 1, 2014
    Assignee: CMC Magnetics Corporation
    Inventors: Yung-Hui Hung, Cheng-Pi Lee, Kun-Long Li, Min-Hao Pan
  • Publication number: 20140054653
    Abstract: An integrated circuit device and a process for making the integrated circuit device. The integrated circuit device including a substrate having a trench formed therein, a first layer of isolation material occupying the trench, a second layer of isolation material formed over the first layer of isolation material, an epitaxially-grown silicon layer on the substrate and horizontally adjacent the second layer of isolation material, and a gate structure formed on the epitaxially-grown silicon, the gate structure defining a channel.
    Type: Application
    Filed: August 24, 2012
    Publication date: February 27, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Min Hao Hong, You-Hua Chou, Chih-Tsung Lee, Shiu-Ko JangJian, Miao-Cheng Liao, Hsiang-Hsiang Ko, Chen-Ming Huang
  • Publication number: 20140044165
    Abstract: A method and apparatus for decoding two-level scanned transform coefficients corresponding to a transform unit (TU) are disclosed. The TU is divided into sub-blocks and the transform coefficients of the TU are scanned across the sub-blocks according to a first scan pattern, and each sub-block is scanned according to a second scan pattern. In one embodiment, the sub-blocks of the transform coefficients received from the variable length decoding are stored in an inverse scan buffer (or TC buffer) and the transform coefficients are retrieved from the inverse scan buffer row-by-row or column-by-column in a selected direction after a corresponding row or column of the transform coefficients is fully received. In a system incorporating an embodiment of the present invention, at least a leading row or a leading column of the transform coefficients is available in the selected direction before a last sub-block of the transform coefficients arrives.
    Type: Application
    Filed: March 1, 2013
    Publication date: February 13, 2014
    Applicant: MEDIATEK INC.
    Inventors: Min-Hao Chiu, Yung-Chang Chang
  • Publication number: 20140030866
    Abstract: A method for depositing a polysilazane on a semiconductor wafer is provided. The method includes steps of disposing a silazane onto the semiconductor wafer, and heating the silazane to form the polysilazane on the semiconductor wafer. An apparatus for preparing a polysilazane on a semiconductor wafer is also provided.
    Type: Application
    Filed: July 25, 2012
    Publication date: January 30, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: You-Hua Chou, Chih-Tsung Lee, Min-Hao Hong, Ming-Huei Lien, Chih-Jen Wu, Chen-Ming Huang
  • Patent number: D701991
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: April 1, 2014
    Assignee: ABL IP Holding, LLC
    Inventors: Darren Blum, Michael Trung Tran, Peter Y. Y. Ngai, Min-Hao Michael Lu
  • Patent number: D715478
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: October 14, 2014
    Assignee: ABL IP Holding, LLC
    Inventors: Darren Blum, Michael Trung Tran, Peter Y. Y. Ngai, Min-Hao Michael Lu