Abstract: Aspects of the present inventive concept provide a semiconductor device capable of enhancing performance and reliability through source/drain engineering in a transistor including an oxide semiconductor layer. The semiconductor device includes a substrate, a metal oxide layer disposed on the substrate, a source/drain pattern being in contact with the metal oxide layer and including a portion protruding from a top surface of the metal oxide layer, a plurality of gate structures disposed on the metal oxide layer with the source/drain pattern interposed therebetween and each including gate spacers and an insulating material layer, the insulating material layer being in contact with the metal oxide layer, and not extending along a top surface of the source/drain pattern, and a contact disposed on the source/drain pattern, the contact being connected to the source/drain pattern.

Abstract: A color conversion member includes: a first sub-partition part having a width which decreases from a first surface toward a second surface; a second sub-partition part disposed on the first sub-partition part and having a width which increases from the first sub-partition part toward the second surface; and a partition part which is disposed on the second sub-partition part and includes a liquid-repellent part including a liquid-repellent additive.

Abstract: A deburring tool includes: a body; and a cutting unit provided on an end portion of the body and including a blade part, where a first channel is provided inside the body, and when a fluid supplied from outside of the deburring tool through the first channel is injected into the cutting unit and presses the cutting unit, the cutting unit moves and a degree to which the blade part protrudes outwardly increases.

Abstract: A semiconductor memory device including: a stack structure including a plurality of layers that are vertically stacked on a substrate, each of the plurality of layers including a word line, a channel layer, and a data storage element electrically connected to the channel layer; and a bit line that vertically extends on one side of the stack structure, wherein the word line includes: a first conductive line that extends in a first direction; and a gate electrode that protrudes in a second direction from the first conductive line, the second direction intersecting the first direction, wherein the channel layer is on the gate electrode, and wherein the bit line includes a connection part electrically connected to the channel layer.

Abstract: A semiconductor device includes an active fin on a substrate, a gate electrode and intersecting the active fin, gate spacer layers on both side walls of the gate electrode, and a source/drain region in a recess region of the active fin at at least one side of the gate electrode. The source/drain region may include a base layer in contact with the active fin, and having an inner end and an outer end opposing each other in the first direction on an inner sidewall of the recess region. The source/drain region may include a first layer on the base layer. The first layer may include germanium (Ge) having a concentration higher than a concentration of germanium (Ge) included in the base layer. The outer end of the base layer may contact the first layer, and may have a shape convex toward outside of the gate electrode on a plane.

Abstract: A display device includes a substrate on which an active region and a non-active region disposed are defined. The non-active region at least partially surrounds the active region. A light-emitting element is disposed in the active region on the substrate. An encapsulation layer is disposed on the light-emitting element. Block patterns are disposed in the non-active region on the substrate and at least partially surround the active region. The non-active region includes a first non-active region positioned at a first side of the active region and a second non-active region positioned at a second side of the active region. There are more block patterns disposed in the first non-active region than in the second non-active region.

Abstract: Provided is a semiconductor memory device comprising a bit line extending in a first direction, a channel pattern on the bit line and including a first oxide semiconductor layer in contact with the bit line and a second oxide semiconductor layer on the first oxide semiconductor layer, wherein each of the first and second oxide semiconductor layers includes a horizontal part parallel to the bit line and first and second vertical parts that vertically protrude from the horizontal part, first and second word lines between the first and second vertical parts of the second oxide semiconductor layer and on the horizontal part of the second oxide semiconductor layer, and a gate dielectric pattern between the channel pattern and the first and second word lines. A thickness of the second oxide semiconductor layer is greater than that of the first oxide semiconductor layer.

Abstract: A composition contains 45-65 weight-percent (wt %) of a linear polyorganosiloxane with terminal vinyl functionality, 39 wt % to less than 50 wt % alkenyl-free polyorganosiloxane resin comprising R3SiO1/2 and SiO4/2 siloxane units at an average molar ratio of greater than zero to 10; where R is independently in each occurrence selected from a group consisting of alkyl groups containing from one to 10 carbon atoms; 0.5-15 wt % mercapto-functional linear polyorganosiloxane crosslinker; 0.01-0.1 wt % radical stabilizer; 0.01-3 wt % thiol-ene photopolymerization initiator; 0-10 wt % fumed silica; and 0-5 wt % polydimethylsiloxane; wherein weight-percent values are relative to composition weight, the composition has a molar ratio of SiH/vinyl functional groups that is greater than 0.3 and at the same time less than 0.

Abstract: A semiconductor device includes a substrate, a peripheral circuit layer, a first active pattern, a gate electrode, a first insulating layer, a conductive contact, and a second active pattern. The peripheral circuit layer is disposed on the substrate, and the peripheral circuit layer includes logic transistors and an interconnection layer that is disposed on the logic transistors. The first active pattern is disposed on the peripheral circuit layer. The gate electrode is disposed on a channel region of the first active pattern. The first insulating layer is disposed on the first active pattern and the gate electrode. The conductive contact is disposed in the first insulating layer and is electrically connected to a first source/drain region of the first active pattern, and the second active pattern is disposed on the first insulating layer. The channel region of the second active pattern vertically overlaps with the conductive contact.

Abstract: A semiconductor device includes a substrate, an oxide semiconductor film on the substrate, a first gate structure on the oxide semiconductor film and a contact that is in contact with the oxide semiconductor film, the contact being disposed on a boundary surface with the oxide semiconductor film, and including a metal oxide film that includes a transition metal.

Abstract: Provided are a cosmetic composition for inhibiting sebum hypersecretion and a method of inhibiting sebum hypersecretion using the same. According to the present invention, there may be provided the cosmetic composition of inhibiting and adjusting sebum secretion which is harmless to the human body with excellent skin safety and decreases activity of peroxisome proliferator activated receptor gamma (PPAR-?) to fundamentally decrease sebum overproduction, thereby providing the skin with an effective effect, and a method of using the same.

Abstract: The display panel includes an upper display substrate including a plurality of pixel areas and a light blocking area, a lower display substrate. The upper display substrate includes a base substrate, a barrier part overlapping the light blocking area and disposed on the base substrate, a light blocking layer including a first light blocking portion disposed on the barrier part and a second light blocking portion disposed on the same layer as the barrier part to respectively overlap the pixel areas, a reflection layer including a first reflection portion disposed on the first light blocking portion and a second reflection portion disposed on the second light blocking portion, and a light control layer overlapping the pixel areas and disposed on the reflection layer. A plurality of openings passing through the second light blocking portion and the second reflection portion are defined in each of the pixel areas.

Abstract: A semiconductor device may include a first active fin, a plurality of second active fins, a first source/drain layer structure, and a second source/drain layer structure. The first active fin may be on a first region of a substrate. The second active fins may be on a second region of the substrate. The first and second gate structures may be on the first and second active fins, respectively. The first source/drain layer structure may be on a portion of the first active fin that is adjacent to the first gate structure. The second source/drain layer structure may commonly contact upper surfaces of the second active fins adjacent to the second gate structure. A top surface of the second source/drain layer structure may be further from the surface of the substrate than a top surface of the first source/drain layer structure is to the surface of the substrate.

Abstract: Provided is a pharmaceutical composition including irinotecan free base. The pharmaceutical composition according to the presently claimed subject matter enables the effective oral administration of irinotecan and as such, can increase the convenience of administration of irinotecan and provide a high in vivo absorption rate, compared to conventional injections.

Abstract: Disclosed is a memory device including a row decoder generating word line (WL) control signals based on a row address from an external device, a first sub-array including memory cells connected to word lines, a first sub-word line driver (SWD) providing a selection voltage or a non-selection voltage to odd-numbered word lines of the word lines based on odd-numbered WL control signals corresponding to the odd-numbered word lines, and a second SWD providing the selection voltage or the non-selection voltage to even-numbered word lines of the word lines based on even-numbered WL control signals corresponding to the even-numbered word lines. The first SWD applies the non-selection voltage to non-selection word lines of the even-numbered word lines, in response to the even-numbered WL control signals, and the second SWD applies the non-selection voltage to non-selection word lines of the odd-numbered word lines, in response to the odd-numbered WL control signals.

Abstract: Provided is a pharmaceutical composition for oral administration in the form of powder obtained by a process including: (a) preparing an emulsion including zanamivir as an active ingredient; triglyceride; acyl glycerol; a nonionic surfactant; a sugar; and water; and (b) lyophilizing the emulsion prepared in the step (a). The pharmaceutical composition according to the presently claimed subject matter can significantly increase in vivo absorption rate of zanamivir. Further, the pharmaceutical composition according to the presently claimed subject matter is in the form of powder, which not only make it easy to store and distribute but also make it possible to avoid the use of functional packaging materials for preventing changes in moisture.

Abstract: A display device includes a light emitting diode electrically connected between a driving voltage line and a common voltage line; a driving transistor electrically connected between the driving voltage line and the light emitting diode; a second transistor electrically connected between a first electrode of the driving transistor electrically connected to the driving voltage line and a data line; a first scan line electrically connected to a gate electrode of the second transistor; a third transistor electrically connected between a second electrode of the driving transistor electrically connected to the light emitting diode and a gate electrode of the driving transistor; and a connection electrode that connects the gate electrode of the driving transistor and the third transistor, wherein at least a part of a contact portion where the connection electrode contacts the third transistor does not overlap the first scan line.

Abstract: The present invention relates to an artificially engineered CRISPR/Cas9 system. More particularly, the present invention relates to an artificially engineered CRISPR enzyme having enhanced target specificity and a use of an artificially engineered CRISPR/Cas9 system including the same enzyme in genome and/or epigenome manipulation or modification, genome targeting, genome editing, and in vitro diagnosis, etc.

Abstract: A display device and method of manufacturing same includes: a display panel having a pixel area and a peripheral area adjacent to the pixel area, a light control layer disposed on the display panel and at least partially overlapping the pixel area, a light blocking portion at least partially overlapping the peripheral area, and a protective layer disposed between the light control layer and the light blocking portion.