Abstract: A method for forming a semiconductor device is disclosed. A substrate including a gate dielectric layer and a gate electrode layer sequentially formed thereon is provided. An offset spacer is formed on sidewalls of the gate dielectric layer and the gate electrode layer. A carbon spacer is formed on a sidewall of the offset spacer, and the carbon spacer is then removed. The substrate is implanted to form a lightly doped region using the gate electrode layer and the offset spacer as a mask. The method may also include providing a substrate having a gate dielectric layer and a gate electrode layer sequentially formed thereon. A liner layer is formed on sidewalls of the gate electrode layer and on the substrate. A carbon spacer is formed on a portion of the liner layer adjacent the sidewall of the gate electrode layer. A main spacer is formed on a sidewall of the carbon spacer. The carbon spacer is removed to form an opening between the liner layer and the main spacer.

Abstract: A logic switch intentionally utilizes GIDL current as its primary mechanism of operation. Voltages may be applied to a doped gate overlying and insulated from a pn junction. A first voltage initiates GIDL current, and the logic switch is bidirectionally conductive. A second voltage terminates GIDL current, but the logic switch is unidirectionally conductive. A third voltage renders the logic switch bidirectionally non-conductive. Circuits containing the logic switch are also described. These circuits include inverters, SRAM cells, voltage reference sources, and neuron logic switches. The logic switch is primarily implemented according to SOI protocols, but embodiments according to bulk protocols are described.

Abstract: Disclosed are atomic layer deposition method and a semiconductor device including the atomic layer, including the steps: placing a semiconductor substrate in an atomic layer deposition chamber; feeding a first precursor gas to the semiconductor substrate within the chamber to form a first discrete monolayer on the semiconductor substrate; feeding an inert purge gas to the semiconductor substrate within the chamber to remove the first precursor gas which has not formed the first discrete monolayer on the semiconductor substrate; feeding a second precursor gas to the chamber to react with the first precursor gas which has formed the first discrete monolayer, forming a discrete atomic size islands; and feeding an inert purge gas to the semiconductor substrate within the chamber to remove the second precursor gas which has not reacted with the first precursor gas and byproducts produced by the reaction between the first and the second precursor gases.

Abstract: The present disclosure provides a green transistor for nano-Si Ferro-electric random access memory (FeRAM) and method of operating the same. The nano-Si FeRAM includes a plurality of memory cells arranged in an array with bit-lines and word-lines, and each memory cell includes a MOSFET including a gate, a source, a drain, a substrate, and a data storage element formed on the drain spacer of the gate and made of nano-Si in porous SiO2; a word-line connected to the gate; a first bit-line connected to the drain; a second bit-line connected to the source; and an substrate bias supply connected to the substrate, and the gate induced drain leakage current of the MOSFET serves as the read current of the memory cell.

Abstract: A semiconductor non-volatile memory (NVM) device, comprising: a semiconductor substrate; a three-layer stack structure of medium layer-charge trapping layer-medium layer disposed on the semiconductor substrate; a gate disposed above the three-layer stack structure; a source and a drain disposed in the semiconductor substrate at either side of the three-layer stack structure; wherein the charge trapping layer is a dielectric layer containing one or more discrete compound clusters formed by atomic layer deposition (ALD) method.

Abstract: A random access memory includes a plurality of memory cells arrayed in bit-lines and word-lines. Each memory cell comprises a green transistor (gFET) including a gate, a source, and a drain; a switching resistor including a first terminal and a second terminal; and a reference resistor including a third terminal and a fourth terminal. The first terminal of the switching resistor and the third terminal is connected to a bit-line, the second terminal of the switching resistor is connected to the first source of the gFET, the fourth terminal of the reference resistor is connected to the second source of the gFET, and the gate of the gFET is connected to a word-line.

Abstract: There is provided a method of manufacturing a semiconductor device, including the following steps: flowing a first precursor gas to the semiconductor substrate within a ALD chamber to form a first discrete monolayer on the semiconductor substrate; flowing an inert purge gas to the semiconductor substrate within the ALD chamber; flowing a second precursor gas to the ALD chamber to react with the first precursor gas which has formed the first monolayer, thereby forming a first discrete compound monolayer; and flowing an inert purge gas; forming a first dielectric layer to cover the discrete compound monolayer; forming a second third monolayer above first dielectric layer; and forming a second discrete compound monolayer; and forming a second dielectric layer to cover the second discrete compound monolayer above the first dielectric layer. There is also provided a semiconductor device formed by the ALD method.

Abstract: A method for forming a semiconductor device is disclosed. A substrate including a gate dielectric layer and a gate electrode layer sequentially formed thereon is provided. An offset spacer is formed on sidewalls of the gate dielectric layer and the gate electrode layer. A carbon spacer is formed on a sidewall of the offset spacer, and the carbon spacer is then removed. The substrate is implanted to form a lightly doped region using the gate electrode layer and the offset spacer as a mask. The method may also include providing a substrate having a gate dielectric layer and a gate electrode layer sequentially formed thereon. A liner layer is formed on sidewalls of the gate electrode layer and on the substrate. A carbon spacer is formed on a portion of the liner layer adjacent the sidewall of the gate electrode layer. A main spacer is formed on a sidewall of the carbon spacer. The carbon spacer is removed to form an opening between the liner layer and the main spacer.

Abstract: A method for forming a semiconductor device is disclosed. A substrate including a gate dielectric layer and a gate electrode layer sequentially formed thereon is provided. An offset spacer is formed on sidewalls of the gate dielectric layer and the gate electrode layer. A carbon spacer is formed on a sidewall of the offset spacer, and the carbon spacer is then removed. The substrate is implanted to form a lightly doped region using the gate electrode layer and the offset spacer as a mask. The method may also include providing a substrate having a gate dielectric layer and a gate electrode layer sequentially formed thereon. A liner layer is formed on sidewalls of the gate electrode layer and on the substrate. A carbon spacer is formed on a portion of the liner layer adjacent the sidewall of the gate electrode layer. A main spacer is formed on a sidewall of the carbon spacer. The carbon spacer is removed to form an opening between the liner layer and the main spacer.

Abstract: The present disclosure provides a green transistor for nano-Si Ferro-electric random access memory (FeRAM) and method of operating the same. The nano-Si FeRAM includes a plurality of memory cells arranged in an array with bit-lines and word-lines, and each memory cell includes a MOSFET including a gate, a source, a drain, a substrate, and a data storage element formed on the drain spacer of the gate and made of nano-Si in porous SiO2; a word-line connected to the gate; a first bit-line connected to the drain; a second bit-line connected to the source; and an substrate bias supply connected to the substrate, and the gate induced drain leakage current of the MOSFET serves as the read current of the memory cell.

Abstract: A random access memory includes a plurality of memory cells arrayed in bit-lines and word-lines. Each memory cell comprises a green transistor (gFET) including a gate, a source, and a drain; a switching resistor including a first terminal and a second terminal; and a reference resistor including a third terminal and a fourth terminal. The first terminal of the switching resistor and the third terminal is connected to a bit-line, the second terminal of the switching resistor is connected to the first source of the gFET, the fourth terminal of the reference resistor is connected to the second source of the gFET, and the gate of the gFET is connected to a word-line.

Abstract: A resistive random access memory utilizing gate induced drain leakage current as the read operation current and the write operation current and a method of operation the same, wherein the resistive random access memory including a plurality of arrayed memory cells, a plurality of bit-lines and a plurality word-lines, each memory cell including: a switching resistor having a first terminal and a second terminal, the first terminal of the switching resistor being connected to one bit-line; and a MOSFET being connected to the second terminal and having a gate, a source, a drain and a substrate, the gate being connected to one word-line, the read operation current and the write operation current of the memory cell being gate induced drain leakage current of the MOSFET. The RRAM array presented in this invention has superior scalability for resistors as well as transistors, which leads to a memory array with higher density.

Abstract: The present invention provides a bipolar transistor, a method for forming the bipolar transistor, a method for turning on the bipolar transistor, and a band-gap reference circuit, virtual ground reference circuit and double band-gap reference circuit with the bipolar transistor. The bipolar transistor includes: a Silicon-On-Insulator wafer; a base area, an emitter area and a collector area; a base area gate dielectric layer on a top silicon layer and atop the base area; a base area control-gate on the base area gate dielectric layer; an emitter electrode connected to the emitter area via a first contact; a collector electrode connected to the collector area via a second contact; and a base area control-gate electrode connected to the base area control-gate via a third contact.

Abstract: A vertical resistor. A substrate includes a trench filled by an isolation layer. A first doped-type region and a second doped-type region are formed on both sides of the trench. The first doped-type region receives a control bias, the second doped-type region receives a reference bias, and a resistance between the second doped-type region and the substrate is adjusted in response to a voltage difference between the control bias and the reference bias.

Abstract: A CMOS device is provided. A semiconductor device comprises a substrate, the substrate having a first region and a second region, the first region having a first crystal orientation represented by a family of Miller indices comprising {i,j,k}, the second region having a second crystal orientation represented a family of Miller indices comprising {l,m,n}, wherein l2+m2+n2>i2+j2+k2. Alternative embodiments further comprise an NMOSFET formed on the first region, and a PMOSFET formed on the second region. Embodiments further comprise a Schottky contact formed with at least one of a the NMOSFET or PMOSFET.

Abstract: There is provided a method of manufacturing a semiconductor device, including the following steps: flowing a first precursor gas to the semiconductor substrate within the ALD chamber to form a first discrete monolayer on the semiconductor substrate; flowing an inert purge gas to the semiconductor substrate within the ALD chamber; flowing a second precursor gas to the ALD chamber to react with the first precursor gas which has formed the first monolayer, thereby forming a first discrete compound monolayer; and flowing an inert purge gas; and forming a second discrete compound monolayer above the semiconductor substrate by the same process as that for forming the first discrete compound monolayer. There is also provided a semiconductor device in which the charge trapping layer is a dielectric layer containing the first and second discrete compound monolayers formed by the ALD method.

Abstract: A logic switch intentionally utilizes GIDL current as its primary mechanism of operation. Voltages may be applied to a doped gate overlying and insulated from a pn junction. A first voltage initiates GIDL current, and the logic switch is bidirectionally conductive. A second voltage terminates GIDL current, but the logic switch is unidirectionally conductive. A third voltage renders the logic switch bidirectionally non-conductive. Circuits containing the logic switch are also described. These circuits include inverters, SRAM cells, voltage reference sources, and neuron logic switches. The logic switch is primarily implemented according to SOI protocols, but embodiments according to bulk protocols are described.

Abstract: A logic switch intentionally utilizes GIDL current as its primary mechanism of operation. Voltages may be applied to a doped gate overlying and insulated from a pn junction. A first voltage initiates GIDL current, and the logic switch is bidirectionally conductive. A second voltage terminates GIDL current, but the logic switch is unidirectionally conductive. A third voltage renders the logic switch bidirectionally non-conductive. Circuits containing the logic switch are also described. These circuits include inverters, SRAM cells, voltage reference sources, and neuron logic switches. The logic switch is primarily implemented according to SOI protocols, but embodiments according to bulk protocols are described.

Abstract: Disclosed herein is a DRAM memory cell featuring a reduced size, increased retention time, and compatibility with standard logic manufacturing processes, making it well-suited for use as embedded DRAM. The memory cell disclosed herein includes a pass-gate transistor and a storage region. The transistor includes a gate and a drain. The storage region includes a trench, which is preferably a Shallow Trench Isolation (STI). A non-insulating structure, e.g., formed of polysilicon or metal, is located in the trench as serves as a capacitor node. The trench is partially defined by a doped sidewall that serves as a source for the transistor. The poly structure and the trench sidewall are separated by a dielectric layer. The write operation involves charge transport to the non-insulating structure by direct tunneling through the dielectric layer. The read operation is assisted by Gate Induced Drain Leakage (GIDL) current generated on the surface of the sidewall.

Abstract: A 2-bit FinFET flash memory cell capable of storing 2 bits and a method of forming the same are provided. The memory cell includes a semiconductor fin on a top surface of a substrate, a gate insulation film on the top surface and sidewalls of a channel section of the semiconductor fin, a gate electrode on the gate insulation film, and two charge-trapping regions along opposite sides of the gate electrode, wherein each charge-trapping region is separated from the gate electrode and the semiconductor fin by a tunneling layer. The memory cell further includes a protective layer on the charge-trapping regions. Each of the two charge-trapping regions is capable of storing one bit. The memory cell can be operated by applying different bias voltages to the source, the drain, and the gate of the memory cell.