Abstract: An image sensor is provided. The image sensor can include a semiconductor substrate including a circuit region, an interlayer dielectric including a metal interconnection on the semiconductor substrate, a lower electrode on the metal interconnection, and a light receiving portion on the lower electrode. The light receiving portion can be a PIN diode formed to have a convex shape.

Abstract: An image sensor according to one embodiment of the present invention includes a semiconductor substrate having a CMOS circuit formed therein; an interlayer dielectric layer formed on the semiconductor substrate and including a trench formed therein; a metal wiring and a first conductive layer formed within the trench of the interlayer dielectric layer; an intrinsic layer formed on the semiconductor substrate including the first conductive layer and the interlayer dielectric layer; and a second conductive layer formed on the intrinsic layer.

Abstract: Provided is a plasma diagnostic apparatus having a probe unit, which is inserted into a plasma or disposed at boundary of a plasma, the apparatus including: a signal supplying unit having a signal supplying source; a current detecting/voltage converting unit for applying a periodic voltage signal applied from the signal supplying unit to the probe unit, detecting the magnitude of the current flowing through the probe unit, and converting the detected current into a voltage; and a by-frequency measurement unit for computing the magnitude and phase of individual frequency components of the current flowing through the probe unit by receiving the voltage output from the current detecting/voltage converting unit as an input.

Abstract: A wiring structure, a semiconductor device having the structure, and a method for manufacturing the semiconductor device are disclosed. The wiring structure includes a first metal layer, a second metal layer on the first metal layer, an insulating layer between the first metal layer and the second metal layer, and a metal via pattern formed in the insulating layer to electrically connect the first and second metal layers to each other. The metal via pattern includes a plurality of metal vias spaced apart from one another, and each of the metal vias includes a vertical via line extending in a vertical direction and a horizontal via line extending in a horizontal direction to cross the vertical via line. The wiring structure may achieve minimized chip defects, fewer cracks in the insulating layer, effective use of the occupation area of a semiconductor chip, and reduced chip size and manufacturing costs.

Abstract: An image sensor and fabricating method thereof are provided. A multi-layered interlayer insulating layer is formed on a substrate including a photodiode, and a metal line is formed in the interlayer insulating layer, such that the metal line passes through the interlayer insulating layer. A conductive barrier layer is formed on the metal line, a color filter array is formed on the interlayer insulating layer and the metal line, and microlenses are formed on the color filter array.

Abstract: Disclosed is a multinuclear transition metal half metallocene catalyst having a multinuclear half metallocene structure in which a transition metal of groups 3 to 10 on periodic table is connected to a cycloalkandienyl group or its derivative group on a side and also connected to phenol or phenolamine compound having a plurality of binding sites on another side. The metallocene catalyst is useful to produce syndiotatic styrene polymer having superior steroreguality, high melting point and broad molecular weight distribution with high activity together with a small amount of a cocatalyst. Further disclosed is a method for preparing styrene polymers using the same catalyst.

Abstract: The present invention relates to a transition metal half metallocene catalyst with a noble structure for preparing syndiotatic styrene polymer having high activity, superior stereoregularity, high melting point and broad molecular weight distribution and a process for preparing styrene polymer using the same. The present invention provides a half metallocene catalyst having a single nucleus structure, in which a transition metal in Groups 3 to 10 on the periodic table is connected to a cycloalkanedienyl group or its derivative forming 5-coordinate bond on a side thereof and to any one of triethanolamine, N-alkyldiethanolamine and N-dialkylethanolamine group, all of which have a plurality of binding sites and high steric hinderance, on the other side thereof. The noble metallocene catalyst according to the present invention is useful for preparing highly syndiotatic vinyl aromatic polymer with broad molecular weight distribution and high activity.

Abstract: A method of bonding a wafer in a system in package is provided. A plating layer is formed on each of a first semiconductor substrate and a second semiconductor substrate. The plating layers are then bonded to each other to connect the semiconductor substrates.

Abstract: Provided are a semiconductor chip, a method of fabricating a semiconductor chip, and a semiconductor chip stack package. The semiconductor chip includes a semiconductor substrate and a semiconductor device on the semiconductor substrate. A dielectric covers the semiconductor device. A top metal is on the dielectric and electrically connected to the semiconductor device. A deep via penetrates the semiconductor substrate and the dielectric. An interconnection connects the deep via and the top metal electrically. A bump is in contact with the top metal and the interconnection.

Abstract: The present invention relates to a method for preparing a styrenic olefin. The method of the present invention comprises the steps of: adding a catalyst and a solvent in a reactor and heating the reactor to create a reflux state; adding an alcohol starting material to the reactor dropwise at a constant rate; removing water generated by adding the alcohol starting material from the reactor, and purifying the obtained styrenic olefin. The method of the present invention is advantageous in minimizing byproducts and preparing styrenic olefins having a variety of substituents in high yield.

Abstract: Provided are an image sensor and a method of manufacturing the same. The image sensor can be vertically arranged image sensor where the photodiode is provided above the circuitry on the substrate. The photodiode can be formed on a lower electrode provided electrically connected to a CMOS circuit on a substrate. The photodiode can have a PIN or PI photodiode structure including an intrinsic layer on the lower electrode and a conductive type layer on the intrinsic layer. A salicide layer can be disposed on the intrinsic layer, and the conductive type conduction layer can be disposed on the salicide layer. The intrinsic layer can be formed to create a light condensing portion, providing a convex-shaped upper surface.

Abstract: A semiconductor chip may include a wafer, a semiconductor device formed on the wafer, a first dielectric layer formed on the wafer and the semiconductor device, a first metal interconnection formed on the first dielectric layer, a second dielectric layer formed on the first dielectric layer and the lower interconnection, and a third dielectric layer formed on the second dielectric layer. A second metal interconnection may be formed in the third dielectric layer, a first nitride layer formed on the third dielectric layer and the first metal interconnection, a via hole extending through the wafer, the first dielectric layer, the second dielectric layer, the third dielectric layer and the first nitride layer, a via formed in the via hole and a third metal interconnection formed on the first oxide layer, an exposed upper end of the via and the second metal interconnection.

Abstract: A method of manufacturing a semiconductor device including at least one of the following steps: Forming an insulating film having at least one trench on and/or over a semiconductor substrate. Forming a metal film on and/or over a surface of an insulating film, including inside the trench. Forming a metal seed layer on and/or over the metal film inside the trench. Forming a metal plating layer on and/or over the metal seed layer to fill the trench.

Abstract: An image sensor includes a semiconductor substrate having a pixel region and a peripheral circuit region. An interlayer dielectric layer has metal wirings and a pad formed over the semiconductor substrate. A lower electrode is selectively formed over the metal wirings. A photo diode is formed over the interlayer dielectric layer of the pixel region. An upper electrode formed over the photo diode. Therefore, a vertical integration of the transistor and the photodiode may approach a fill factor to 100%, and provide higher sensitivity, implement more complicated circuitry without reducing sensitivity in each unit pixel, improve the reliability of the image sensor by preventing crosstalk, etc., between the pixels, and improve light sensitivity by increasing the surface area of the photo diode in the unit pixel.

Abstract: An image sensor according to one embodiment of the present invention includes a semiconductor substrate having a CMOS circuit formed therein; an interlayer dielectric layer formed on the semiconductor substrate and including a trench formed therein; a metal wiring and a first conductive layer formed within the trench of the interlayer dielectric layer; an intrinsic layer formed on the semiconductor substrate including the first conductive layer and the interlayer dielectric layer; and a second conductive layer formed on the intrinsic layer.

Abstract: A method for fabricating a metal pad is disclosed. The fabrication method includes the step of selectively etching a wire insulation film formed on a semiconductor substrate to form a pattern, such as a dual damascene pattern, having plural vias in one trench. A metal film is deposited to fill the pattern and an insulation film is formed on the metal film. Further, the method includes removing the insulation film and the metal film to expose a surface of the wire insulation film to thereby form a metal pad and via contacts.

Abstract: Provided is a plasma diagnostic apparatus includes a probe unit, which is inserted into a plasma or disposed at boundary of a plasma, the apparatus includes: a signal supplying unit having a signal supplying source; a current detecting/voltage converting unit for applying a periodic voltage signal applied from the signal supplying unit to the probe unit, detecting the magnitude of the current flowing through the probe unit, and converting the detected current into a voltage; and a by-frequency measurement unit for computing the magnitude and phase of individual frequency components of the current flowing through the probe unit by receiving the voltage output from the current detecting/voltage converting unit as an input.

Abstract: Disclosed is an image sensor which includes a plurality of pixel patterns formed on corresponding metal interconnections of an interlayer dielectric and a dummy pixel pattern formed between adjacent pixel patterns of the plurality of the pixel patterns. The dummy pixel patterns are not formed connected to the metal interconnections. The dummy pixel patterns can be formed spaced a distance apart from the plurality of pixel patterns such that air gaps form between the dummy pixel patterns and the pixel patterns in an intrinsic layer that is formed on the dummy pixel pattern and the plurality of pixel patterns.

Abstract: An image sensor is provided. The image sensor can include a semiconductor substrate including a circuit region, an interlayer electric including a metal interconnection on the semiconductor substrate, a lower electrode on the metal interconnection, and a light receiving portion on the lower electrode. The light receiving portion can be a PIN diode formed to have a convex shape.

Abstract: An image sensor is disclosed including a second semiconductor substrate including a metal interconnection and a second interlayer dielectric; a second via penetrating the second interlayer dielectric so that the second via is connected to the metal interconnection; a first semiconductor substrate on the second interlayer dielectric, the first semiconductor substrate having a unit pixel; a pre-metal dielectric on the first semiconductor substrate; a first via penetrating the pre-metal dielectric and the first semiconductor substrate, the first via being electrically connected to the second via; a first interlayer dielectric on the pre-metal dielectric including the first via; a metal interconnection on the first interlayer dielectric and connected to the first via and the unit pixel; a conductive barrier layer on the metal interconnection; and a color filter and a microlens on the first interlayer dielectric in each unit pixel.