Abstract: A method of bonding a wafer in a system in package is provided. A plating layer is formed on each of a first semiconductor substrate and a second semiconductor substrate. The plating layers are then bonded to each other to connect the semiconductor substrates.

Abstract: Provided are a semiconductor chip, a method of fabricating a semiconductor chip, and a semiconductor chip stack package. The semiconductor chip includes a semiconductor substrate and a semiconductor device on the semiconductor substrate. A dielectric covers the semiconductor device. A top metal is on the dielectric and electrically connected to the semiconductor device. A deep via penetrates the semiconductor substrate and the dielectric. An interconnection connects the deep via and the top metal electrically. A bump is in contact with the top metal and the interconnection.

Abstract: The present invention relates to a method for preparing a styrenic olefin. The method of the present invention comprises the steps of: adding a catalyst and a solvent in a reactor and heating the reactor to create a reflux state; adding an alcohol starting material to the reactor dropwise at a constant rate; removing water generated by adding the alcohol starting material from the reactor, and purifying the obtained styrenic olefin. The method of the present invention is advantageous in minimizing byproducts and preparing styrenic olefins having a variety of substituents in high yield.

Abstract: Provided are an image sensor and a method of manufacturing the same. The image sensor can be vertically arranged image sensor where the photodiode is provided above the circuitry on the substrate. The photodiode can be formed on a lower electrode provided electrically connected to a CMOS circuit on a substrate. The photodiode can have a PIN or PI photodiode structure including an intrinsic layer on the lower electrode and a conductive type layer on the intrinsic layer. A salicide layer can be disposed on the intrinsic layer, and the conductive type conduction layer can be disposed on the salicide layer. The intrinsic layer can be formed to create a light condensing portion, providing a convex-shaped upper surface.

Abstract: A semiconductor chip may include a wafer, a semiconductor device formed on the wafer, a first dielectric layer formed on the wafer and the semiconductor device, a first metal interconnection formed on the first dielectric layer, a second dielectric layer formed on the first dielectric layer and the lower interconnection, and a third dielectric layer formed on the second dielectric layer. A second metal interconnection may be formed in the third dielectric layer, a first nitride layer formed on the third dielectric layer and the first metal interconnection, a via hole extending through the wafer, the first dielectric layer, the second dielectric layer, the third dielectric layer and the first nitride layer, a via formed in the via hole and a third metal interconnection formed on the first oxide layer, an exposed upper end of the via and the second metal interconnection.

Abstract: A method of manufacturing a semiconductor device including at least one of the following steps: Forming an insulating film having at least one trench on and/or over a semiconductor substrate. Forming a metal film on and/or over a surface of an insulating film, including inside the trench. Forming a metal seed layer on and/or over the metal film inside the trench. Forming a metal plating layer on and/or over the metal seed layer to fill the trench.

Abstract: An image sensor includes a semiconductor substrate having a pixel region and a peripheral circuit region. An interlayer dielectric layer has metal wirings and a pad formed over the semiconductor substrate. A lower electrode is selectively formed over the metal wirings. A photo diode is formed over the interlayer dielectric layer of the pixel region. An upper electrode formed over the photo diode. Therefore, a vertical integration of the transistor and the photodiode may approach a fill factor to 100%, and provide higher sensitivity, implement more complicated circuitry without reducing sensitivity in each unit pixel, improve the reliability of the image sensor by preventing crosstalk, etc., between the pixels, and improve light sensitivity by increasing the surface area of the photo diode in the unit pixel.

Abstract: A method for fabricating a metal pad is disclosed. The fabrication method includes the step of selectively etching a wire insulation film formed on a semiconductor substrate to form a pattern, such as a dual damascene pattern, having plural vias in one trench. A metal film is deposited to fill the pattern and an insulation film is formed on the metal film. Further, the method includes removing the insulation film and the metal film to expose a surface of the wire insulation film to thereby form a metal pad and via contacts.

Abstract: An image sensor according to one embodiment of the present invention includes a semiconductor substrate having a CMOS circuit formed therein; an interlayer dielectric layer formed on the semiconductor substrate and including a trench formed therein; a metal wiring and a first conductive layer formed within the trench of the interlayer dielectric layer; an intrinsic layer formed on the semiconductor substrate including the first conductive layer and the interlayer dielectric layer; and a second conductive layer formed on the intrinsic layer.

Abstract: Provided is a plasma diagnostic apparatus includes a probe unit, which is inserted into a plasma or disposed at boundary of a plasma, the apparatus includes: a signal supplying unit having a signal supplying source; a current detecting/voltage converting unit for applying a periodic voltage signal applied from the signal supplying unit to the probe unit, detecting the magnitude of the current flowing through the probe unit, and converting the detected current into a voltage; and a by-frequency measurement unit for computing the magnitude and phase of individual frequency components of the current flowing through the probe unit by receiving the voltage output from the current detecting/voltage converting unit as an input.

Abstract: Disclosed is an image sensor which includes a plurality of pixel patterns formed on corresponding metal interconnections of an interlayer dielectric and a dummy pixel pattern formed between adjacent pixel patterns of the plurality of the pixel patterns. The dummy pixel patterns are not formed connected to the metal interconnections. The dummy pixel patterns can be formed spaced a distance apart from the plurality of pixel patterns such that air gaps form between the dummy pixel patterns and the pixel patterns in an intrinsic layer that is formed on the dummy pixel pattern and the plurality of pixel patterns.

Abstract: An image sensor is provided. The image sensor can include a semiconductor substrate including a circuit region, an interlayer electric including a metal interconnection on the semiconductor substrate, a lower electrode on the metal interconnection, and a light receiving portion on the lower electrode. The light receiving portion can be a PIN diode formed to have a convex shape.

Abstract: Disclosed is an image sensor, which includes a substrate having a transistor circuit and lower interconnections. First interconnections are formed separated from each other on the substrate and electrically connected to the CMOS circuitry through the lower interconnections. Planarized insulating layers are formed between the first interconnections to isolate unit pixels. An intrinsic layer is formed on the substrate including the insulating layers, and a second conductive layer is formed on the intrinsic layer. The first interconnections, the intrinsic layer and the second conductive layer provide a photodiode structure for the image sensor.

Abstract: An image sensor is disclosed including a second semiconductor substrate including a metal interconnection and a second interlayer dielectric; a second via penetrating the second interlayer dielectric so that the second via is connected to the metal interconnection; a first semiconductor substrate on the second interlayer dielectric, the first semiconductor substrate having a unit pixel; a pre-metal dielectric on the first semiconductor substrate; a first via penetrating the pre-metal dielectric and the first semiconductor substrate, the first via being electrically connected to the second via; a first interlayer dielectric on the pre-metal dielectric including the first via; a metal interconnection on the first interlayer dielectric and connected to the first via and the unit pixel; a conductive barrier layer on the metal interconnection; and a color filter and a microlens on the first interlayer dielectric in each unit pixel.

Abstract: A semiconductor device, and method for manufacturing a device with selective copper plating in a deep via. The method comprises etching a plurality of deep trenches in the surface of wafer, sequentially forming an insulating layer, a copper anti-diffusion layer, a metal layer, and a copper seed layer over the surface and deep trenches of the wafer, performing a first planarization process in order to remove the copper seed layer on the surface of wafer while retaining the copper seed layer in the deep trenches of the wafer, and forming a plurality of via patterns by copper plating the copper seed layer remaining in the deep trenches of the wafer.

Abstract: An image sensor and fabricating method thereof are provided. A multi-layered interlayer insulating layer is formed on a substrate including a photodiode, and a metal line is formed in the interlayer insulating layer, such that the metal line passes through the interlayer insulating layer. A conductive barrier layer is formed on the metal line, a color filter array is formed on the interlayer insulating layer and the metal line, and microlenses are formed on the color filter array.

Abstract: A via plating system and method are provided. A preprocessing procedure is performed such that a pre-wetting solution is absorbed into a via hole, forming a wetting layer thereon. A plating process is then performed to form a plating layer inside the via hole. The preprocessing procedure to form the wetting layer improves the absorbing characteristics inside the via hole, allowing the plating layer to be more effectively formed.

Abstract: Disclosed is a display driving chip of a semiconductor chip. According to an embodiment, the display driving chip comprises, input/output (I/O) pads each electrically connected to a lower interconnection on an active area, the I/O pads forming a perimeter on an inner peripheral surface of the active area, and dummy pads formed on the active area within the perimeter of I/O pads.

Abstract: A method of bonding a wafer in a system in package is provided. A plating layer is formed on each of a first semiconductor substrate and a second semiconductor substrate. The plating layers are then bonded to each other to connect the semiconductor substrates.

Abstract: An apparatus and method for partitioning a hard disk drive (HDD), more particularly an apparatus and method for partitioning the HDD into a desired number of partitions of a desired size without requiring a reboot once user registration has been completed. The apparatus includes an input unit that receives user registration and partition configuration information, a state-check unit that checks the state of a master partition, a hidden-partition-checking unit that checks the number of hidden partitions in order to determine whether the execution of partition is achievable if the result of the check shows that the master partition is in in-progress state, and a partition-execution unit that executes partitioning a slave partition based on the input partition-configuration information if the result of the check shows that execution of the partition is achievable.