Abstract: Disclosed is a method of processing cyber threat information including disassembling an input file to acquire analysis target functions in assembly code, calculating a function hash value for each of quantized function vectors of the analysis target functions, determining at least one candidate function from pre-stored comparison target functions based on the calculated function hash value, and classifying cyber threat information for the analysis target functions based on similarity for the at least one candidate function.

Abstract: A cyber threat information processing method including receiving a CTI analysis request for a document script from a client; analyzing the document script to obtain analysis information of the CTI for the script; generating a CTI query related to the document script based on the analysis information of the CTI and delivering the CTI query to a natural language model; and providing natural language description information according to the CTI query from the analysis information of the CTI and the natural language model to the client.

Abstract: Provided is a cyber threat information processing method including receiving a CTI analysis request for a file from a client; analyzing the file to obtain analysis information of the CTI for the file; generating a CTI query related to the file based on the analyzed CTI and delivering the CTI query to a natural language model; and providing natural language description information according to the CTI query obtained from the CTI for the analyzed file and the natural language model.

Abstract: Provided is a cyber threat information processing method including receiving a CTI analysis request for assembly code from a client; analyzing the assembly code to obtain analysis information of the CTI for the assembly code; generating a CTI query related to a file based on the analyzed CTI and delivering the CTI query to a natural language model; and providing natural language description information according to the CTI query obtained from the CTI for the assembly code and the natural language model.

Abstract: An image sensor comprises a first and second chips. The first chip includes a first semiconductor substrate, a photoelectric conversion layer in the first semiconductor substrate, a color filter, a micro lens, a first transistor adjacent to the photoelectric conversion layer, a first insulating layer, and a first metal layer in the first insulating layer and connected to the first transistor. The second chip includes a second insulating layer, a second semiconductor substrate, a second transistor on the second semiconductor substrate, a second metal layer in the second insulating layer and connected to a gate structure of the second transistor through a gate contact, a landing metal layer below the second metal layer, and a through via in direct contact with the landing metal layer and vertically passing through the second semiconductor substrate. A width of the through via becomes narrower as the width approaches the third surface.

Abstract: A semiconductor device includes an address input circuit configured to boost a voltage level of at least one bit of a row address to generate a boosting address and to drive a signal of a first node based on other bits of the row address and the boosting address. The semiconductor device also includes a word line selection signal generation circuit configured to drive a signal of a second node based on the signal of the first node and to generate a word line selection signal for selecting a word line based on the signal of the second node.

Abstract: Discussed are an apparatus for measuring a thickness of a unit cell of a battery, and a method of measuring the thickness of the unit cell of the battery. The apparatus includes a plurality of transfer rollers configured to sequentially transfer unit cells, and disposed to be the plurality of transfer rollers being spaced a predetermined distance from each other; and a thickness sensor disposed at a fixed position to irradiate light to a moving path of the unit cells and calculate a time when receiving taken to receive the light that is reflected light from the unit cells, thereby measuring a thickness of each of the unit cells.

Abstract: Provided is a cyber threat information processing method including acquiring webpage data based on link information, and analyzing tag structure information of the webpage data, converting data included in a tag area of the webpage data into tag feature data according to the tag structure information, and training an AI model using the converted tag feature data to acquire cyber threat information of the data included in the tag area.

Abstract: Provided is a cyber threat information processing method including collecting a webpage and classifying data included in the webpage or data linked according to link depth, detecting whether the data included in the webpage or the linked data is malicious on a plurality of layers, the plurality of layers including at least two of antivirus-based malicious pattern detection, signature malicious pattern detection according to a certain rule, or malignancy detection according to an artificial intelligence (AI) algorithm for the data, and providing or storing record data of the webpage when the data is detected to be malicious as a result of the detection.

Abstract: Provided is a cyber threat information processing method including obtaining disassembled code by dissembling an executable file, generating an instruction sequence based on a control flow according to a relationship between instructions in the disassembled code, converting the generated instruction sequence into a feature data set related to a cyber threat, and acquiring cyber threat information by learning the feature data set using an artificial intelligence (AI) model.

Abstract: The present disclosure relates to an electrode stack for a lithium secondary battery, in which one or more positive electrodes and one or more negative electrodes are alternatingly stacked with a separator therebetween and insulation layers are formed on the outermost positive electrodes of the electrode stack. The insulation layers have an average thickness of 1 ?m to 8 ?m. The positive electrodes include a positive electrode collector; a positive electrode active material layer; and a protective layer including an inorganic compound. The protective layer is disposed between the positive electrode collector and the positive electrode active material layer. Additionally, an electrode assembly and a lithium secondary battery which include the electrode stack are also disclosed.

Abstract: A cyber threat information processing method including generating stack trace information of a reader program of an operating system executing a non-executable file at a hooking point of a system call of the operating system when the reader program performs the system call, obtaining a calling function for calling the system call and a variable corresponding to the calling function from the generated stack trace information, and providing description information about the obtained calling function and the variable corresponding to the calling function.

Abstract: Provided is a cyber threat information processing method including receiving input of a non-executable file, analyzing at least one feature related to a cyber threat of the input non-executable file, and generating analysis information, detecting whether the non-executable file includes a malicious action based on feature information obtained by selectively combining at least one piece of the generated analysis information, generating classification information on an attack technique and classification information on an attack group according to a malicious action when the malicious action is detected in the non-executable file, and providing cyber threat information to a user based on generated information of the non-executable file.

Abstract: An image sensor includes: a substrate including a first surface and a second surface on which light is incident, the second surface being opposite to the first surface; a photoelectric converter provided in the substrate; a first metal layer provided on the first surface of the substrate; a second metal layer provided on the first metal layer; and a capacitor layer provided between the first metal layer and the second metal layer, wherein the capacitor layer includes: a first lower electrode electrically connected to the first metal layer, a first upper electrode electrically connected to the second metal layer, a second upper electrode spaced apart from the first upper electrode and electrically connected to the second metal layer, a first capacitor provided between the first lower electrode and the first upper electrode, and a second capacitor provided between the first lower electrode and the second upper electrode.

Abstract: An image sensor device including: a first digital pixel including a first photodetector and first memory cells to store a first digital signal corresponding to a first output from the first photodetector; and a second digital pixel including a second photodetector and second memory cells to store a second digital signal corresponding to a second output from the second photodetector, the second digital pixel is adjacent to one side of the first digital pixel, the first memory cells and the second memory cells are connected with a plurality of bit lines, the first memory cells are connected with a first word line and a third word line, the second memory cells are connected with a second word line and a fourth word line, the second word line is between the first and third word lines, and the third word line is between the second and fourth word lines.

Abstract: An image sensor and a method for fabricating the same are provided. The image sensor includes a substrate including a first surface opposite a second surface that is incident to light, a first photoelectric conversion layer in the substrate, a wiring structure including a plurality of wiring layers on the first surface of the substrate, an interlayer insulating film on the second surface of the substrate, a capacitor structure in the interlayer insulating film, and a first wiring on the interlayer insulating film. The capacitor structure includes a first conductive pattern, a dielectric pattern, and a second conductive pattern sequentially stacked on the second surface of the substrate. The second conductive pattern is connected to the first wiring.

Abstract: An image sensor device including: a first digital pixel including a first photodetector and first memory cells to store a first digital signal corresponding to a first output from the first photodetector; and a second digital pixel including a second photodetector and second memory cells to store a second digital signal corresponding to a second output from the second photodetector, the second digital pixel is adjacent to one side of the first digital pixel, the first memory cells and the second memory cells are connected with a plurality of bit lines, the first memory cells are connected with a first word line and a third word line, the second memory cells are connected with a second word line and a fourth word line, the second word line is between the first and third word lines, and the third word line is between the second and fourth word lines.

Abstract: A semiconductor device includes an address input circuit configured to boost a voltage level of at least one bit of a row address to generate a boosting address and to drive a signal of a first node based on other bits of the row address and the boosting address. The semiconductor device also includes a word line selection signal generation circuit configured to drive a signal of a second node based on the signal of the first node and to generate a word line selection signal for selecting a word line based on the signal of the second node.

Abstract: An image sensor is provided. The image sensor includes a substrate including a plurality of unit pixels, each of unit pixels includes a photoelectric conversion element; a first trench formed in the substrate in a lattice shape to isolate the plurality of unit pixels; a plurality of first capacitor structures extended along a sidewall of the first trench in the first trench, including a first electrode, a second electrode, and a first dielectric layer between the first electrode and the second electrode; and a first capacitor isolation pattern at a lattice point of the first trench to isolate the plurality of first capacitor structures.

Abstract: An electronic device includes an intelligent refresh control circuit generating an intelligent refresh pulse with a pulse that has a generation period that is adjusted based on the number of generations of an auto refresh signal during an intelligent refresh operation, and an internal refresh signal generation circuit outputting one of a self-refresh pulse including a pulse that is periodically generated by an enable signal during a self-refresh operation and the intelligent refresh pulse as an internal refresh signal.