Abstract: A sound-reproducing method that includes the steps outlined below is provided. A playback sound is generated by applying original audio into a test environment. The playback sound is received to generate received sound data. At least one test environment spatial parameter corresponding to the test environment is calculated according to known audio data related to the original audio and the received sound data. Input audio is modified by applying the test environment spatial parameter thereto to generate reproduced audio.

Abstract: A wearable device includes a frame and a display element is provided. The frame internally includes a sliding element. The display element is attached to the sliding element and can slide on the sliding element to be brought in front of the wearer's eye or away from the wearer's eye.

Abstract: An echo-cancelling device includes an audio input/output (I/O) terminal, an audio-receiving module, an analog-to-digital (A/D) converter, and a processor is provided. The A/D converter is electrically connected to the audio-receiving module. The processor is electrically connected to the A/D converter and the audio I/O terminal. The audio I/O terminal receives an external reference signal from an electronic device. The audio-receiving module receives an input audio and an output audio from the electronic device, and generates an analog input signal having the input audio and the output audio. The A/D converter generates a digital input signal according to the analog input signal. The processor cancels the output audio to generate a second (digital) sound signal according to the digital input signal and the external reference signal. Finally, the processor transmits the second (digital) sound signal to the electronic device via the audio I/O terminal.

Abstract: The disclosure provides an audio processing device, an audio processing method for controlling a plurality of speakers, and a computer program product. The audio processing device includes a memory, a transceiver, and a processor. The memory stores a plurality of modules. The transceiver is wirelessly paired with a plurality of speakers. The processor executes the modules to perform following steps: requesting each of the speakers to output an audio positioning signal; collecting the audio positioning signal from each of the speakers; retrieving a location of each of the speakers relative to the audio processing device according to the audio positioning signal from each of the speakers; adjusting a plurality of audio contents based on the location of each of the speakers relative to the audio processing device; and sending the audio contents to the speakers to control the speakers outputting the audio contents.

Abstract: Some embodiments relate to a semiconductor device. The semiconductor device includes a layer disposed over a substrate. A conductive body extends through the layer. A plurality of bar or pillar structures are spaced apart from one another and laterally surround the conductive body. The plurality of bar or pillar structures are generally concentric around the conductive body.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a metal-oxide-semiconductor (MOS) transistor, and a dielectric layer. The MOS transistor includes a gate structure formed over the substrate. The dielectric layer is formed aside the gate structure, and the dielectric layer is doped with a strain modulator. An effective lattice constant of the dielectric layer doped with the strain modulator is different from an original lattice constant of the dielectric layer prior to be doped with the strain modulator, wherein the strain modulator at least comprises silicon.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a first fin structure over a semiconductor substrate. The semiconductor device structure also includes a second fin structure over the semiconductor substrate. The second fin structure has a lower height than that of the first fin structure. The second fin structure includes a first sidewall and a second sidewall, and the first sidewall and the second sidewall surround a recess over the second fin structure.

Abstract: Methods for forming a semiconductor structure are provided. The method includes forming a first dummy gate structure and forming first spacers over a sidewall of the first dummy gate structure. The method includes removing the first dummy gate structure to form a first trench between the first spacers and forming a first capping layer in the first trench. A first portion of the first capping layer covers a sidewall of the first trench and a second portion of the first capping layer covers a bottom surface of the first trench. The method further includes oxidizing a sidewall of the first portion of the first capping layer and a top surface of the second portion of the first capping layer to form a first capping oxide layer and forming a first work function metal layer and forming a first gate electrode layer over the first work function metal layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a first source region, a second source region, a first drain region, and a second drain region. The semiconductor device structure includes a first gate structure over the substrate and between the first source region and the first drain region. The semiconductor device structure includes a second gate structure over the substrate and between the second source region and the second drain region. A first thickness of the first gate structure is greater than a second thickness of the second gate structure. A first gate width of the first gate structure is less than a second gate width of the second gate structure.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a first source region, a second source region, a first drain region, and a second drain region. The semiconductor device structure includes a first gate structure over the substrate and between the first source region and the first drain region. The semiconductor device structure includes a second gate structure over the substrate and between the second source region and the second drain region. A first thickness of the first gate structure is greater than a second thickness of the second gate structure. A first gate width of the first gate structure is less than a second gate width of the second gate structure.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a metal-oxide-semiconductor (MOS) transistor, and a dielectric layer. The MOS transistor includes a gate structure formed over the substrate. The dielectric layer is formed aside the gate structure, and the dielectric layer is doped with a strain modulator. An effective lattice constant of the dielectric layer modified by the doping with the strain modulator is different from an effective lattice constant of the dielectric layer prior to the doping.

Abstract: A wireless charging guide system includes a wireless charging cradle, an electronic device and a visual guide medium. The electronic device includes a power storage unit and a charging unit. When the visual guide medium guides the electronic device to be placed at a first position on the top surface of the wireless charging cradle, the charging unit, with respect to the wireless charging cradle, has a charging rate larger than a first default value and starts to charge the power storage unit, wherein the visual guide medium is accessed from a remote server according to the model of the electronic device.

Abstract: A semiconductor device includes a substrate, an isolation structure, and a gate structure. The substrate has an active area. The isolation structure surrounds the active area of the substrate. The gate structure is across the active area of the substrate. The isolation structure has a first portion under the gate structure and a second portion adjacent to the gate structure. A top surface of the first portion of the isolation structure is lower than a top surface of the second portion of the isolation structure.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a gate structure formed over the substrate. The gate structure includes a gate dielectric layer formed over the substrate and a capping layer formed over the gate dielectric layer. The gate structure further includes a capping oxide layer formed over the capping layer and a work function metal layer formed over the capping oxide layer. The gate structure further includes a gate electrode layer formed over the work function metal layer.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a metal gate electrode structure and an insulating layer over the semiconductor substrate. The insulating layer surrounds the metal gate electrode structure. The method includes nitrifying a first top portion of the metal gate electrode structure to form a metal nitride layer over the metal gate electrode structure.

Abstract: A semiconductor device with the metal fuse is provided. The metal fuse connects an electronic component (e.g., a transistor) and a existing dummy feature which is grounded. The protection of the metal fuse can be designed to start at the beginning of the metallization formation processes. The grounded dummy feature provides a path for the plasma charging to the ground during the entire back end of the line process. The metal fuse is a process level protection as opposed to the diode, which is a circuit level protection. As a process level protection, the metal fuse protects subsequently-formed circuitry. In addition, no additional active area is required for the metal fuse in the chip other than internal dummy patterns that are already implemented.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate stack over a semiconductor substrate. The semiconductor device structure also includes a source/drain structure over the semiconductor substrate, and the source/drain structure includes a dopant. The semiconductor device structure further includes a channel region under the gate stack. In addition, the semiconductor device structure includes a semiconductor layer surrounding the source/drain structure. The semiconductor layer is configured to prevent the dopant from entering the channel region.

Abstract: The semiconductor device includes a substrate, an epi-layer, a first etch stop layer, an interlayer dielectric (ILD) layer, a second etch stop layer, a protective layer, a liner, a silicide cap and a contact plug. The substrate has a first portion and a second portion. The epi-layer is disposed in the first portion. The first etch stop layer is disposed on the second portion. The ILD layer is disposed on the first etch stop layer. The second etch stop layer is disposed on the ILD layer, in which the first etch stop layer, the ILD layer and the second etch stop layer form a sidewall surrounding the first portion. The protective layer is disposed on the sidewall. The liner is disposed on the protective layer. The silicide cap is disposed on the epi-layer. The contact plug is disposed on the silicide cap and surrounded by the liner.

Abstract: A method for controlling a battery to charge or discharge includes detecting a usage pattern of the electronic device. The battery includes a first battery and a second battery. A state-of-charge (SOC) value of the fist battery and a SOC value of the second battery are acquired, and a processor of the electronic device can control the first battery and/or the second battery to charge and discharge the electronic device according to the usage pattern and the SOC value.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate, an interfacial layer formed over the substrate, and an insertion layer formed over the interfacial layer. The semiconductor structure further includes a gate dielectric layer formed over the insertion layer and a gate structure formed over the gate dielectric layer. The insertion layer and the gate dielectric layer may be metal oxides where the insertion layer has an oxygen coordination number greater than the gate dielectric layer.