Patents by Inventor Min Lin

Min Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12252494
    Abstract: Crystalline Forms of Compound (I): pharmaceutically acceptable salts thereof and solvates of any of the foregoing are disclosed. Pharmaceutical compositions comprising the same, methods of treating disorders and conditions associated with oncogenic KIT and PDGFRA alterations using the same, and methods for making Compound (I) and crystalline forms thereof are also disclosed.
    Type: Grant
    Filed: December 8, 2022
    Date of Patent: March 18, 2025
    Assignee: Blueprint Medicines Corporation
    Inventors: Brenton Mar, Anthony L. Boral, Hui-Min Lin, Hongliang Shi
  • Publication number: 20250088606
    Abstract: Aspects of the present disclosure involve a system comprising a computer-readable storage medium storing a program and method for recreating keyboard and mouse sounds within a virtual working environment. The program and method provide for receiving, from a first client device of a first participant of a group of participants within a virtual working environment, a timing of keyboard and mouse input detected at the client device, the group of participants having been selected from among plural participants of the virtual working environment; generating, in response to the receiving, keyboard and mouse sounds that correspond to the timing of the keyboard and mouse input; and providing the generated keyboard and mouse sounds to one or more second client devices of respective one or more second participants of the group of participants, for presentation on the one or more second client devices.
    Type: Application
    Filed: November 22, 2024
    Publication date: March 13, 2025
    Inventors: Brandon Francis, Andrew Cheng-min Lin, Walton Lin
  • Publication number: 20250087625
    Abstract: A zone heater assembly of a reflow solder tool includes a gas deflector having a single-layer structure. The single-layer structure may include one or more gas-permeating patterns through which a process gas is to flow from one or more gas outlets to a gas exhaust of the zone heater assembly. The one or more gas-permeating patterns in the single-layer structure promote uniformity of gas flow through the gas exhaust and into a heating zone of the reflow solder tool. The uniformity of the gas flow of the process gas enables convection heat provided by the process gas to be uniformly distributed across the heating zone. In this way, the gas deflector described herein may decrease hot spots and/or cold spots in the heating zone, which enables greater flexibility in placement of semiconductor package substrates on a conveyor device of the reflow solder tool.
    Type: Application
    Filed: January 11, 2024
    Publication date: March 13, 2025
    Inventors: Yu-Young WANG, Chun-Min LIN, Min-Yu WU, Chih-Jen WU
  • Patent number: 12249526
    Abstract: A device may detect a semiconductor wafer to be transferred from a source wafer carrier to a target wafer carrier, and may cause a light source to illuminate the semiconductor wafer. The device may cause a camera to capture images of the semiconductor wafer after the light source illuminates the semiconductor wafer, and may perform image recognition of the images of the semiconductor wafer to determine whether an edge of the semiconductor wafer is damaged. The device may cause the semiconductor wafer to be provided to the source wafer carrier when the edge of the semiconductor wafer is determined to be damaged, and may cause the semiconductor wafer to be provided to the target wafer carrier when the edge of the semiconductor wafer is determined to be undamaged.
    Type: Grant
    Filed: March 6, 2023
    Date of Patent: March 11, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen Min Lin, Hsien Tse Chen
  • Publication number: 20250079227
    Abstract: A wafer retaining device is provided. The wafer retaining device includes a platen configured to support a semiconductor wafer, and a retainer assembly. The retainer assembly includes a mounting member coupled to the platen, a lever, and a biasing member including a first end coupled to the lever and a second end coupled to the mounting member. The biasing member is configured to bias the lever to a closed position relative to the platen. The lever inhibits movement of the semiconductor wafer when the lever is in the closed position.
    Type: Application
    Filed: January 18, 2024
    Publication date: March 6, 2025
    Inventors: Lu-Hsun LIN, Tsung-Min LIN, Chin Tsung LIN, Hsiao-Yin HSIEH, Po-Tang TSENG
  • Publication number: 20250081393
    Abstract: A joint module for cutting coolant circuit in a server comprises a base, a first moving piece, a second moving piece, a drive component, and a plug connector located on the first moving piece. The first moving piece is movable in a first direction between a first position and a second position. The second moving piece is movable in a second direction between a third position and a fourth position. The drive component moves the second moving piece. When the second moving piece is on the third position, the first moving piece is on the first position and the plug connector is connected to a plug. When the second moving piece is on the fourth position, the first moving piece is on the second position and the plug connector is disconnected with the plug. A server and a computing system with the joint module are also disclosed.
    Type: Application
    Filed: May 15, 2024
    Publication date: March 6, 2025
    Inventors: CHANG-JU WU, CHIH-MIN LIN
  • Patent number: 12244966
    Abstract: Aspects of the present disclosure involve a system comprising a computer-readable storage medium storing a program and method for providing template rooms within a virtual conferencing system. The program and method provide for providing an interface to configure a template room for virtual conferencing; receiving, via the interface, an indication of user input specifying a configuration for the template room; accessing a data file comprising values for generating plural rooms based on the configuration for the template room; and providing, based on the configuration for the template room and on the data file, for virtual conferencing between plural participants across the plural rooms.
    Type: Grant
    Filed: September 29, 2022
    Date of Patent: March 4, 2025
    Assignee: Snap Inc.
    Inventors: Andrew Cheng-min Lin, Walton Lin
  • Patent number: 12243577
    Abstract: A memory system includes a memory device and a processing device coupled to the memory device. The processing device receives a plurality of codewords; determines that one or more codewords of the plurality of codewords are corrupt; selects a first read voltage associated with the one or more codewords, such that the first read voltage is based on a second read voltage utilized for reading the one or more codewords in a previous read operation; and applies the first read voltage to a set of memory cells storing the one or more corrupted codewords.
    Type: Grant
    Filed: September 5, 2023
    Date of Patent: March 4, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Yi-Min Lin, Fangfang Zhu, Chih-Kuo Kao
  • Patent number: 12243707
    Abstract: The current disclosure is directed to a repellent electrode used in a source arc chamber of an ion implanter. The repellent electrode includes a shaft and a repellent body having a repellent surface. The repellent surface has a surface shape that substantially fits the shape of the inner chamber space of the source arc chamber where the repellent body is positioned. A gap between the edge of the repellent body and the inner sidewall of the source arc chamber is minimized to a threshold level that is maintained to avoid a short between the conductive repellent body and the conductive inner sidewall of the source arc chamber.
    Type: Grant
    Filed: August 10, 2023
    Date of Patent: March 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Heng Yen, Jen-Chung Chiu, Tai-Kun Kao, Lu-Hsun Lin, Tsung-Min Lin
  • Patent number: 12241688
    Abstract: A vapor-phase/liquid-phase fluid heat exchange unit includes: a first cover body having a first and a second side, a vapor outlet and a liquid inlet, the vapor outlet and the liquid inlet being in communication with the first and second sides; and a second cover body having a third and a fourth side, the first and second cover bodies being correspondingly mated with each other to together define a heat exchange space. A working fluid and a fluid separation unit are disposed in the heat exchange space. The fluid separation unit partitions the heat exchange space into an evaporation section corresponding to the vapor outlet and a backflow section corresponding to the liquid inlet.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: March 4, 2025
    Assignee: ASIA VITAL COMPONENTS CO., LTD.
    Inventors: Chih-Peng Chen, Yu-Min Lin
  • Patent number: 12242313
    Abstract: A system determines a current state of an information handling system, and receives a sensor output signal. The system determines whether a status change of the sensor output signal relates to an expected state based on the current state and a previous state of the information handling system, and determines whether the sensor output signal is triggered by an external magnet. If the status change of the sensor output signal relates to the expected state and the sensor output signal is not triggered by the external magnet, then the system transitions the information handling system from the current state to the expected state.
    Type: Grant
    Filed: September 28, 2023
    Date of Patent: March 4, 2025
    Assignee: Dell Products L.P.
    Inventors: Chen Hsin Chang, Wan Shih Chien, Yi Min Lin
  • Publication number: 20250070969
    Abstract: A micro-controller including a secure world, a non-secure world, and a processing circuit is provided. The secure world includes a key management device, a decryption circuit, and a first memory. The key management device stores a secret key. The decryption circuit utilizes the secret key to decrypt an encrypted model to generate a decrypted model. The first memory stores the decrypted model. The non-secure world includes a second memory and a third memory. The second memory stores the encrypted model. The third memory stores an inference result. The processing circuit provides input data to the decrypted model. The decrypted model generates the inference result according to the input data.
    Type: Application
    Filed: July 24, 2024
    Publication date: February 27, 2025
    Inventor: Zong-Min LIN
  • Publication number: 20250068774
    Abstract: A micro-controller including a non-secure world, a secure world, and a processing circuit is provided. The non-secure world stores a neural network model including an encrypted operator and an un-encrypted operator. The secure world stores a key and includes a decryption circuit. In a non-secure mode, the processing circuit interprets the un-encrypted operator. In a secure mode, the processing circuit directs the decryption circuit to use the key to decrypt the encrypted operator to generate a decrypted result. In the secure mode, the processing circuit interprets the decrypted result to generate second output data and stores the second output data in the non-secure world.
    Type: Application
    Filed: July 24, 2024
    Publication date: February 27, 2025
    Inventor: Zong-Min LIN
  • Publication number: 20250063715
    Abstract: A method for forming a semiconductor memory structure includes forming a bottom electrode layer over an active region, depositing a first high-k dielectric material on the bottom electrode layer, depositing a second high-k dielectric material on the first high-k dielectric material, annealing the first and second high-k dielectric materials, after the annealing process, depositing a third high-k dielectric material on the second high-k dielectric material, and forming a top electrode layer on the third high-k dielectric material.
    Type: Application
    Filed: May 1, 2024
    Publication date: February 20, 2025
    Inventors: Ji-Min LIN, Pin-Hung CHEN
  • Patent number: 12230549
    Abstract: Three-dimensional integrated circuit (3DIC) structures and methods of forming the same are provided. A 3DIC structure includes a semiconductor package, a first package substrate, a molded underfill layer and a thermal interface material. The semiconductor package is disposed over and electrically connected to the first package substrate through a plurality of first bumps. The semiconductor package includes at least one semiconductor die and an encapsulation layer aside the semiconductor die. The molded underfill layer surrounds the plurality of first bumps and a sidewall of the semiconductor package, and has a substantially planar top surface. The CTE of the molded underfill layer is different from the CTE of the encapsulation layer of the semiconductor package. The thermal interface material is disposed over the semiconductor package.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: February 18, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Min Lin, Ching-Hua Hsieh, Chih-Wei Lin, Sheng-Hsiang Chiu, Sheng-Feng Weng, Yao-Tong Lai
  • Patent number: 12227865
    Abstract: A plating apparatus for electroplating a wafer includes a housing defining a plating chamber for housing a plating solution. A voltage source of the apparatus has a first terminal having a first polarity and a second terminal having a second polarity different than the first polarity. The first terminal is electrically coupled to the wafer. An anode is within the plating chamber, and the second terminal is electrically coupled to the anode. A membrane support is within the plating chamber and over the anode. The membrane support defines apertures, wherein in a first zone of the membrane support a first aperture-area to surface-area ratio is a first ratio, and in a second zone of the membrane support a second aperture-area to surface-area ratio is a second ratio, different than the first ratio.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: February 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Che-Min Lin, Hung-San Lu, Chao-Lung Chen, Chao Yuan Chang, Chun-An Kung, Chin-Hsin Hsiao, Wen-Chun Hou, Szu-Hung Yang, Ping-Ching Jiang
  • Patent number: 12224659
    Abstract: A charging device and a safety function control circuit and method thereof are provided. When a charging device is not connected to a load, a converted voltage value of a power connection terminal of the charging device is kept to be lower than a safe voltage value so as to maintain a safe mode. The safety function control circuit includes a first control module and a second control module for constant voltage control. The first control module and the second control module perform matching control on a power conversion circuit of the charging device, and in case of a single fault of one of the control modules, the other module is still capable of keeping the converted voltage value to be less than the safe voltage value. Thus, it is ensured that the safe mode stays functional in case of a concurrency of both a single hardware fault and a single firmware fault.
    Type: Grant
    Filed: January 30, 2023
    Date of Patent: February 11, 2025
    Assignee: FSP TECHNOLOGY INC.
    Inventors: Che-Min Lin, Kuo-Chieh Chan, Kuan-Jung Lee, Chi-Chang Lien, Ching-Chia Chu
  • Patent number: 12218082
    Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.
    Type: Grant
    Filed: November 9, 2023
    Date of Patent: February 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
  • Publication number: 20250039764
    Abstract: In an electronic device provided in the disclosure, an external antenna device includes at least one directional antenna, a wireless communication module is electrically connected to the external antenna device, and a processing circuit is electrically connected to the wireless communication module.
    Type: Application
    Filed: November 5, 2023
    Publication date: January 30, 2025
    Inventors: Jui-Ting CHUANG, Tz-Shiang HUNG, Kai-Min LIN, Yu-Chen LEE, Ming-Hung CHUNG, Yao-Hsun HUANG
  • Patent number: 12212425
    Abstract: Aspects of the present disclosure involve a system comprising a computer-readable storage medium storing a program and method for providing a room preview within a virtual conferencing system. The program and method provide for virtual conferencing between plural participants within a first room of plural rooms, the plural rooms being included within a virtual space for virtual conferencing; and for each of the plural participants, provide a first audio channel associated with audio output of the first room, provide display of a room preview element within the first room, the room preview element corresponding to a live preview of a second room of the plural rooms, and provide a second audio channel associated with audio output of the second room.
    Type: Grant
    Filed: November 2, 2023
    Date of Patent: January 28, 2025
    Assignee: Snap Inc.
    Inventors: Andrew Cheng-min Lin, Walton Lin