Patents by Inventor Min Lin

Min Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10187086
    Abstract: Techniques for reducing the latency for decoding product codewords with minimal hardware architecture changes are described. In an example, multiple decoding procedures are available a system. The system maintains decoding states. Each decoding state corresponds to a constituent codeword of a product codeword and to a decoding procedure. For instance, a BCH decoding state indicates whether the decoding of the respective BCH constituent codeword has previously failed. The decoding of the product codeword depends on the various decoding state. For instance, in a BCH decoding iteration, if a BCH decoding state of a constitutent codeword is set to “failed,” the BCH decoding of that codeword is skipped.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: January 22, 2019
    Assignee: SK Hynix Inc.
    Inventors: Aman Bhatia, Naveen Kumar, Yi-Min Lin, Fan Zhang
  • Publication number: 20180375504
    Abstract: A FET driving circuit includes: inputs into which a DC voltage is inputted; outputs connected to gate and source electrodes of a FET; a switch; a capacitance connected across the switch; and an LC resonance circuit connected in series with the switch across the inputs. A voltage generated across the switch during switching is outputted to drive the FET. The LC resonance circuit has a first connector connected to one input and a second connector connected to the switch, and is configured with a path including an inductance and a path including an inductance and a capacitance. An impedance between the first and second connectors has two resonant frequencies. The impedance has a local maximum at the lower resonant frequency, which is higher than a switching frequency, and a local minimum at the higher resonant frequency, which is around double the switching frequency.
    Type: Application
    Filed: June 25, 2018
    Publication date: December 27, 2018
    Applicant: TDK CORPORATION
    Inventors: Min LIN, Ken MATSUURA
  • Publication number: 20180375503
    Abstract: A FET driving circuit includes: two inputs for inputting a DC voltage; two outputs respectively connected to gate and source electrodes of a FET; a switch; a resonant capacitance connected between both ends of the switch; and an LC resonance circuit connected between the inputs and both ends of the switch. When the two inputs are shorted, frequency characteristics of an impedance of the LC resonance circuit include, in order from a low to a high-frequency side, first to fourth resonant frequencies. The first resonant frequency is higher than a switching frequency of the switch, the second resonant frequency is around double the switching frequency, the fourth resonant frequency is around four times the switching frequency, and the impedance has local maxima at the first resonant frequency and the third resonant frequency and local minima at the second resonant frequency and the fourth resonant frequency.
    Type: Application
    Filed: June 25, 2018
    Publication date: December 27, 2018
    Applicant: TDK CORPORATION
    Inventors: Min LIN, Ken MATSUURA
  • Publication number: 20180375441
    Abstract: A power converter includes: input terminals for inputting a DC voltage; output terminals for outputting an AC voltage; a switch; a first resonant capacitance connected between both ends of the switch; a first LC resonance circuit connected in series with the switch between the output terminals; and a second LC resonance circuit connected between the input terminals and the switch. The first LC resonance circuit includes an inductance and a capacitance in series. When the input terminals are shorted, frequency characteristics of an impedance of the second LC resonance circuit include first to fourth resonant frequencies. The first resonant frequency is higher than a switching frequency of the switch. The second and fourth resonant frequencies are around double and four times the switching frequency. The impedance has local maxima at the first and third resonant frequencies and local minima at the second and fourth resonant frequencies.
    Type: Application
    Filed: June 19, 2018
    Publication date: December 27, 2018
    Applicant: TDK CORPORATION
    Inventors: Min LIN, Ken MATSUURA
  • Patent number: 10164580
    Abstract: A gate bias circuit for a plurality of GaAs amplifier stages is a transistor coupled to a temperature compensation current received from a CMOS control stage. A plurality of pHEMPT amplifier stages are coupled to the gate bias circuit and to a control voltage which switches the amplifier stage. A selectively controlled stage pass transistor enables a current mirror between the gate bias circuit and each stage amplifying transistor. The penultimate pHEMPT amplifier stage is coupled to a CMOS amplifier. A CMOS circuit provides both the temperature compensation current by a proportional to absolute temperature (PTAT) circuit and the control voltage enabling each pHEMPT transistor to receive its input signal in combination with the gate bias voltage.
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: December 25, 2018
    Inventors: James Wang, Yuh-Min Lin, Kun-You Lin
  • Patent number: 10163609
    Abstract: An ion implanter comprises a dissociation chamber in the ion implanter. The dissociation chamber has an input port for receiving a gas and an output port for outputting ions. A vacuum chamber surrounds the dissociation chamber. A plurality of rods or plates of magnetic material are located adjacent to the dissociation chamber on at least two sides of the dissociation chamber. A magnet is magnetically coupled to the plurality of rods or plates of magnetic material. A microwave source is provided for supplying microwaves to the dissociation chamber, so as to cause electron cyclotron resonance in the dissociation chamber to ionize the gas.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Min Lin, Ming-Hsing Li, Fang-Chi Chien, Chao-Li Shih, Hong-Hsing Chou
  • Publication number: 20180362440
    Abstract: A method for enhancing reaction efficiency of a terephthalate plasticizer involves using a homogenizer to fine PTA to slurry having a particle size of 80-110 ?m, and esterifying the PTA slurry with a C6-C10 alcohol in the presence of a titanium-based catalyst. The reactivity is enhanced by more than 37.5%, and the terephthalate plasticizer so synthetized is low-odor and has a purity of more than 99.5% as well as good physical properties such as acid value, color, and index of refraction.
    Type: Application
    Filed: June 14, 2018
    Publication date: December 20, 2018
    Inventors: Te-Chao LIAO, Jung-Jen CHUANG, Hsun-Min LIN
  • Patent number: 10146726
    Abstract: A motherboard an electronic device using the same are provided. The motherboard includes a motherboard and a control chip. The processor is adapted to be inserted to a processor base including a plurality of pins. The pins is divided to defined pins and undefined pins. The processor base includes a plurality of electrical contacts. A first part of the electrical contacts are corresponding to the defined pins, and a second part of the electrical contacts are corresponding to the undefined pins. The control chip determines whether to make the motherboard enter an overclocking operation mode according to a control command. When the motherboard is set to be at the overclocking operation mode, the control chip transmits a control signal to the undefined pins of the processor via the second part of the electrical contacts, and then the processor improves operating efficiency.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: December 4, 2018
    Assignee: ASUSTeK COMPUTER INC.
    Inventors: Ji-Kuang Tan, Yu-Chen Lee, Bing-Min Lin, Ming-Hung Chung
  • Patent number: 10146001
    Abstract: A lighting system including a LED light source, a convex lens, and a light guide post disposed between the LED light source and the convex lens. The light guide post includes a light emitting portion and a light collecting portion connected to the light emitting portion. The light emitting portion has a light guide post-light emitting surface facing the convex lens. The light collecting portion has an internal reflective surface including at least an elliptical surface having a first focal point and a second focal point. The second focal point is located between the first focal point and the convex lens, and the second focal point is located inside the light guide post.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: December 4, 2018
    Assignee: LEXTAR ELECTRONICS CORPORATION
    Inventors: Yu-Min Lin, Tsung-Huan Tsai, Mong-Ea Lin
  • Publication number: 20180342645
    Abstract: Provided is a method of forming gigantic quantum dots including following steps. A first precursor by mixing zinc acetate (Zn(ac)2), cadmium oxide (CdO), a surfactant, and a solvent together and then performing a first heat treatment is provided. The first precursor includes Zn-complex having the surfactant and Cd-complex having the surfactant. A second precursor containing elements S and Se and trioctylphosphine (TOP) is added into the first precursor to form a reaction mixture. A second heat treatment is performed on the reaction mixture and then cooling the reaction mixture to form the gigantic quantum dots in the reaction mixture.
    Type: Application
    Filed: February 2, 2018
    Publication date: November 29, 2018
    Applicant: Unique Materials Co., Ltd.
    Inventors: Pi-Tai Chou, Shang-Wei Chou, Yu-Min Lin, Chin-Cheng Chiang, Chia-Chun Hsieh
  • Publication number: 20180335762
    Abstract: A hierarchical wireless power management system using a remote control device to control multiple slave controllers is disclosed. The control module of the remote control device comprises a processing circuit, a wireless signal transmission circuit, and a storage unit. The wireless signal transmission circuit is adapted for transmitting a control signal to a corresponding slave controller. The storage unit is storing settings related to the slave controllers. The remote control device manage the operations of slave controllers with a capability of doing a group controlling under the hierarchical architecture, based upon settings comprising a hierarchical grouping distribution architecture changeably set by a managing user and respective corresponding identification codes of the slave controllers set by the managing user.
    Type: Application
    Filed: November 6, 2017
    Publication date: November 22, 2018
    Inventors: Chien-Chou LAI, Tz-Min LIN, Ke-Fan FAN, Dy-Cheng WANG
  • Patent number: 10135464
    Abstract: A method for decoding low-density parity check (LDPC) codes, includes computing an initial syndrome of an initial output, obtaining an initial number of unsatisfied checks based on the computed initial syndrome, and when the initial number of unsatisfied checks is greater than zero, computing a reliability value with a parity check, performing a bit flip operation, computing a subsequent syndrome of a subsequent output, and ending decoding when a number of unsatisfied checks obtained based on the computed subsequent syndrome is equal to zero.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: November 20, 2018
    Assignee: SK Hynix Inc.
    Inventors: Chung-Li Wang, Lingqi Zeng, Yi-Min Lin
  • Publication number: 20180329371
    Abstract: A data processing system includes a buffer, a design under checking (DUC), and a self-checking circuit. The buffer is used to buffer data generated from a source device. The DUC is used to perform a designated function upon data read from the buffer when operating under a normal mode. The self-checking circuit is used to apply logic functional checking to the DUC when the DUC operates under a self-checking mode. When the DUC operates under the self-checking mode, the buffer keeps buffering data generated from the source device.
    Type: Application
    Filed: May 9, 2018
    Publication date: November 15, 2018
    Inventors: Huei-Min Lin, Yi-Chang Chen, Chih-Ming Wang, Yung-Chang Chang
  • Patent number: 10129974
    Abstract: A multi-layer circuit structure includes a differential transmission line pair and at least one conductive pattern. The differential transmission line pair includes first and second transmission lines disposed side by side. Each of the first and second transmission lines includes first and second segments connected to each other. An spacing between the two first segments is non-fixed, and an spacing between the two second segments is fixed. A first zone is located between the two first segments, a second zone is opposite to the first zone and located outside the first segment of the first transmission line, and a third zone is opposite to the first zone and located outside the first segment of the second transmission line. The conductive pattern is coplanar with the differential transmission line pair and disposed on at least one of the first, second and third zones.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: November 13, 2018
    Assignees: Industrial Technology Research Institute, First Hi-tec Enterprise Co., Ltd., NEXCOM International Co., Ltd.
    Inventors: Chien-Min Hsu, Min-Lin Lee, Huey-Ru Chang, Hung-I Liu, Ching-shan Chang
  • Publication number: 20180318049
    Abstract: An implant system and a method of forming the implant system including an implant to be implanted into living bone. The implant includes titanium. The implant includes a first surface geometry on a first portion of a surface of the implant and a second surface geometry on a second portion of the surface of the implant. The first surface geometry includes at least a submicron topography including tube-like structures and the second surface geometry includes a first micro-scale topography, a second micro-scale topography superimposed on the first topography, and a submicron topography superimposed on the first and second micro-scale topographies, the submicron topography including the tube-like structures.
    Type: Application
    Filed: July 16, 2018
    Publication date: November 8, 2018
    Inventors: Daniel Mandanici, Zachary B. Suttin, Keng-Min Lin, Olga S. Sanchez
  • Patent number: 10119766
    Abstract: A heat dissipation device includes a housing and a heat pipe. The heat pipe has an open end, which is inserted into an opening on a top side of the housing, such that a heat pipe chamber of the heat pipe is communicated with a housing chamber of the housing and an extended portion extended from the open end of the heat pipe is pressed against a bottom side of the housing, as well as a heat pipe wick structure of the heat pipe is connected to a housing wick structure of the housing, so as to increase heat transfer effect.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: November 6, 2018
    Assignee: Asia Vital Components Co., Ltd.
    Inventors: Yu-Min Lin, Wen-Ji Lan
  • Publication number: 20180316205
    Abstract: A battery power sustainability device includes a switch device and a processing circuit. The processing circuit controls the switch device to establish a parallel connection between a rapid energy storage module and a battery in a start-up mode and disconnect the parallel connection between the rapid energy storage module and the battery after entering a charging mode according to a trigger signal. When a battery-powered system stops operating, the battery-powered system generates a trigger signal to charge the rapid energy storage module. When the battery-powered system starts up, the drawn power of the battery is decreased under the help of the rapid energy storage module that has enough power, such that the using life of the battery is extended and still can achieve a normal start-up function even the battery has lower power and thereby the power of the battery can be used until exhausted completely. By means of detecting the battery performance, users can safely use up all available battery power.
    Type: Application
    Filed: April 20, 2018
    Publication date: November 1, 2018
    Applicant: TEAM YOUNG TECHNOLOGY CO., LTD.
    Inventors: Tz-Min Lin, Cheng-Chung Wang
  • Patent number: 10110132
    Abstract: A switching power supply device generates a DC output voltage based on a DC input voltage, and includes n converter units and a control unit. The control unit executes first driving control that drives k1 (where 0?k1<n) out of the n converter units when the DC output voltage has risen to an upper limit value of the reference voltage range and second driving control that drives k2 (where k1<k2?n) out of the n converter units when the DC output voltage has fallen to a lower limit value of the reference voltage range. During the first driving control, if the DC output voltage Vo reaches a first value above the upper limit value, k1 and k2 are decreased by a value k0. During the second driving control, if the DC output voltage Vo reaches a second value below the lower limit value, k1 and k2 are increased by the value k0.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: October 23, 2018
    Assignee: TDK CORPORATION
    Inventors: Ken Matsuura, Min Lin
  • Publication number: 20180291027
    Abstract: Provided are certain CDK4/6 inhibitors, pharmaceutical compositions thereof, and methods of use therefor.
    Type: Application
    Filed: April 28, 2016
    Publication date: October 11, 2018
    Inventors: Xingdong ZHAO, Tongshuang LI, Haohan TAN, Zhifang CHEN, Ling CHEN, Qihong LIU, Yue RONG, Lijun YANG, Xianlong WANG, Rui TAN, Zuwen ZHOU, Bin LIU, Min LIN, Lihua JIANG, Yanxin LIU, Li LINGHU, Jing SUN, Weibo WANG
  • Patent number: 10096743
    Abstract: Provided are Gigantic quantum dots and a method of forming gigantic quantum dots. Each of the gigantic quantum dots includes a core constituted of CdSe, a shell constituted of ZnS, and an alloy configured between the core and the shell. The core is wrapped by the shell. The alloy constituted of Cd, Se, Zn and S, wherein a content of the Cd and Se gradually decreases from the core to the shell and a content of the Zn and S gradually increases from the core to the shell. A particle size of each of the gigantic quantum dots is equal to or more than 10 nm.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: October 9, 2018
    Assignee: Unique Materials Co., Ltd.
    Inventors: Pi-Tai Chou, Shang-Wei Chou, Yu-Min Lin, Chin-Cheng Chiang, Chia-Chun Hsieh