Patents by Inventor Min Lin

Min Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230418946
    Abstract: A chip capable of authenticating an off-chip debug firmware program and a debug user account is illustrated. The chip runs the secure boot firmware and executes the secure boot process to verify whether the debug firmware program in a signed program loaded from an external storage device may be executed. After the signed program is successfully verified, the chip runs the debug firmware program to execute a debug user authentication algorithm in the signed program, thereby starting a debug user authentication process. After verifying the debug user account of the external debugging tool connected to the chip is a valid debug user account, the debugging tool is allowed to use the debugging function in the chip according to the authority of the debug user.
    Type: Application
    Filed: June 27, 2022
    Publication date: December 28, 2023
    Inventor: ZONG-MIN LIN
  • Patent number: 11854961
    Abstract: A package substrate includes a substrate, an insulating protective layer and an interposer. The substrate has a first surface and a second surface opposing to the first surface. The substrate includes a plurality of first conductive pads embedded in the first surface. The insulating protective layer is disposed on the first surface of the substrate. The insulating protective layer has an opening for exposing the first conductive pads embedded in the first surface of the substrate. The interposer has a top surface and a bottom surface opposing to the top surface. The interposer includes a plurality of conductive vias and a plurality of second conductive pads located on the bottom surface. The interposer is located in a recess defined by the opening of the insulating protective layer and the first surface of the substrate. Each of the second conductive pads is electrically connected to corresponding first conductive pad.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: December 26, 2023
    Assignees: Industrial Technology Research Institute, Unimicron Technology Corp.
    Inventors: Yu-Hua Chen, Wei-Chung Lo, Tao-Chih Chang, Yu-Min Lin, Sheng-Tsai Wu
  • Patent number: 11855796
    Abstract: Aspects of the present disclosure involve a system comprising a computer-readable storage medium storing a program and method for presenting an overview of participant reactions to a virtual conference. The program and method provide for a virtual conference between plural participants; provide, for each of the plural participants, display of reaction buttons which are selectable by the participant to indicate different reactions to the virtual conference; receive indication of selections of the reaction buttons by one or more of the plural participants; store an indication of the selections over time in association with recording the virtual conference; generate a graphical overview of reactions to the virtual conference based on the stored indication of the selections; and provide, for a first participant of the plural participants, display of the graphical overview.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: December 26, 2023
    Assignee: Snap Inc.
    Inventors: Andrew Cheng-min Lin, Walton Lin
  • Patent number: 11855006
    Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
  • Publication number: 20230409211
    Abstract: A method for protecting data in an external memory based on an isolated execution environment is provided. The method is used in a processor in the isolated execution environment of a system-on-a-chip. The method includes: accessing an output command of a main system processor in a main system of the system-on-a-chip; reading first data from a shared memory in the main system according to the output command; encrypting the first data with a private key and generating encrypted first data; and outputting the encrypted first data to the external memory.
    Type: Application
    Filed: June 17, 2022
    Publication date: December 21, 2023
    Inventor: Zong-Min LIN
  • Publication number: 20230410878
    Abstract: A memory system includes a memory device and a processing device coupled to the memory device. The processing device receives a plurality of codewords; determines that one or more codewords of the plurality of codewords are corrupt; selects a first read voltage associated with the one or more codewords, such that the first read voltage is based on a second read voltage utilized for reading the one or more codewords in a previous read operation; and applies the first read voltage to a set of memory cells storing the one or more corrupted codewords.
    Type: Application
    Filed: September 5, 2023
    Publication date: December 21, 2023
    Inventors: Yi-Min Lin, Fangfang Zhu, Chih-Kuo Kao
  • Publication number: 20230401885
    Abstract: Optical sensors and their making methods are described herein. In some embodiments, a described sensing apparatus includes: an image sensor; a collimator above the image sensor, wherein the collimator includes an array of apertures; and an optical filtering layer above the collimator, wherein the optical filtering layer is configured to filter a portion of light to be transmitted into the array of apertures.
    Type: Application
    Filed: August 10, 2023
    Publication date: December 14, 2023
    Inventors: You-Cheng JHANG, Han-Zong PAN, Wei-Ding WU, Jiu-Chun WENG, Hsin-Yu CHEN, Cheng-San CHOU, Chin-Min LIN
  • Publication number: 20230386778
    Abstract: The current disclosure is directed to a repellent electrode used in a source arc chamber of an ion implanter. The repellent electrode includes a shaft and a repellent body having a repellent surface. The repellent surface has a surface shape that substantially fits the shape of the inner chamber space of the source arc chamber where the repellent body is positioned. A gap between the edge of the repellent body and the inner sidewall of the source arc chamber is minimized to a threshold level that is maintained to avoid a short between the conductive repellent body and the conductive inner sidewall of the source arc chamber.
    Type: Application
    Filed: August 10, 2023
    Publication date: November 30, 2023
    Inventors: Ching-Heng YEN, Jen-Chung CHIU, Tai-Kun KAO, Lu-Hsun LIN, Tsung-Min LIN
  • Patent number: 11830700
    Abstract: The current disclosure is directed to a repellent electrode used in a source arc chamber of an ion implanter. The repellent electrode includes a shaft and a repellent body having a repellent surface. The repellent surface has a surface shape that substantially fits the shape of the inner chamber space of the source arc chamber where the repellent body is positioned. A gap between the edge of the repellent body and the inner sidewall of the source arc chamber is minimized to a threshold level that is maintained to avoid a short between the conductive repellent body and the conductive inner sidewall of the source arc chamber.
    Type: Grant
    Filed: March 11, 2022
    Date of Patent: November 28, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Heng Yen, Jen-Chung Chiu, Tai-Kun Kao, Lu-Hsun Lin, Tsung-Min Lin
  • Publication number: 20230379491
    Abstract: Systems and methods herein describe a video compression system. The described systems and methods accesses a sequence of image frames from a first computing device, the sequence of image frames comprising a first image frame and a second image frame, detects a first set of keypoints for the first image frame, transmits the first image frame and the first set of keypoints to a second computing device, detects a second set of keypoints for the second image frame, transmits the second set of keypoints to the second computing device, causes an animated image to be displayed on the second computing device.
    Type: Application
    Filed: August 4, 2023
    Publication date: November 23, 2023
    Inventors: Sergey Demyanov, Andrew Cheng-min Lin, Walton Lin, Aleksei Podkin, Aleksei Stoliar, Sergey Tulyakov
  • Publication number: 20230369848
    Abstract: A power detection circuit is provided. The protection circuit is coupled to a pad and includes a trigger circuit and a discharge circuit. The trigger circuit includes a first transistor of a first conductivity type and a second transistor, also of the first conductivity type, which are coupled in series between the pad and a ground terminal. The trigger circuit detects whether a transient even occurs on the pad. The discharge circuit is coupled between the bonding pad and the ground terminal and controlled by the trigger circuit. In response to the transient event occurring on the bonding pad, the trigger circuit generates a trigger voltage to trigger the discharge circuit to provide a discharge path between the pad and the ground terminal.
    Type: Application
    Filed: May 11, 2022
    Publication date: November 16, 2023
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Jian-Hsing LEE, Yeh-Ning JOU, Chih-Hsuan LIN, Chang-Min LIN, Hwa-Chyi CHIOU
  • Publication number: 20230367010
    Abstract: A light sensor and a control method thereof are disclosed. The light sensor comprises a light-emitting element, a first light-sensing unit and a second light-sensing unit. The light-emitting element generates an emission signal. The light-sensitive characteristic of the first light-sensing unit corresponds to a first wavelength range. The light-sensitive characteristic of the second light-sensing unit corresponds to a second wavelength range, which is different from the first wavelength range. In this way, when the emission signal is reflected by an object and received by the first light-sensing unit and the second light-sensing unit, the type of the object may be determined based on the difference between the signal sensed by the first light-sensing unit and the signal sensed by the second light-sensing unit.
    Type: Application
    Filed: January 24, 2023
    Publication date: November 16, 2023
    Inventors: Yu-Min Lin, Feng-Jung Hsu
  • Publication number: 20230356202
    Abstract: A tin-titanium-silicon molecular sieve, a preparation method and an application thereof are provided. The electron binding energy of framework tin active centers in the tin-titanium-silicon molecular sieve is 488.5 eV or less. In the tin-titanium-silicon molecular sieve, the molar ratio of titanium to silicon is preferably 0.005-0.03, and the molar ratio of tin to silicon is preferably 0.005-0.025. The tin-titanium-silicon molecular sieve of the invention has more catalytic active centers, a lower electron binding energy of framework tin active centers, and an excellent catalytic performance.
    Type: Application
    Filed: August 26, 2021
    Publication date: November 9, 2023
    Inventors: Changjiu XIA, Yujia LIU, Xinxin PENG, Min LIN, Bin ZHU, Xingtian SHU
  • Patent number: 11810847
    Abstract: A package structure includes a redistribution structure and a core substrate. The redistribution structure includes a plurality of connection pads. The core substrate is disposed on the redistribution structure and electrically connected to the plurality of connection pads. The core substrate includes a first interconnection layer and a plurality of conductive terminals. The first interconnection layer has a first region, a second region surrounding the first region, and a third region surrounding the second region, and includes a plurality of bonding pads located in the first region, the second region and the third region. The conductive terminals are electrically connecting the plurality of bonding pads to the plurality of connection pads of the redistribution structure, wherein the plurality of conductive terminals located over the first region, the second region and the third region of the first interconnection layer have different heights.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: November 7, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Liang Chen, Kuan-Lin Ho, Pei-Rong Ni, Chia-Min Lin, Yu-Min Liang, Jiun-Yi Wu
  • Patent number: 11811222
    Abstract: An electrostatic discharge (ESD) protection circuit including a detection circuit, a voltage-divider element, and a discharge element is provided. The detection circuit is coupled between a first power line and a second power line. In response to an ESD event, the detection circuit enables a turn-on signal. The voltage-divider element is coupled between the first power line and a third power line and receives the turn-on signal. The discharge element is coupled between the second and third power lines. In response to the turn-on signal being enabled, the first discharge element discharges an ESD current.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: November 7, 2023
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Yeh-Ning Jou, Chieh-Yao Chuang, Hsien-Feng Liao, Ting-Yu Chang, Chih-Hsuan Lin, Chang-Min Lin, Shao-Chang Huang, Ching-Ho Li
  • Publication number: 20230347561
    Abstract: A molding apparatus is configured for molding a semiconductor device and includes a lower mold and an upper mold. The lower mold is configured to carry the semiconductor device. The upper mold is disposed above the lower mold for receiving the semiconductor device and includes a mold part and a dynamic part. The mold part is configured to cover the upper surface of the semiconductor device. The dynamic part is disposed around a device receiving region of the upper mold and configured to move relatively to the mold part. A molding method and a molded semiconductor device are also provided.
    Type: Application
    Filed: July 4, 2023
    Publication date: November 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Feng Weng, Ching-Hua Hsieh, Chung-Shi Liu, Chih-Wei Lin, Sheng-Hsiang Chiu, Yao-Tong Lai, Chia-Min Lin
  • Publication number: 20230350517
    Abstract: Touch display device includes a first touch electrode, a second touch electrode, and a first touch signal line. First touch electrode is located in a first area of touch display device and is configured to receive a first control signal to generate a first touch signal. Second touch electrode is located in a second area of touch display device and is configured to receive a second control signal to generate a second touch signal. First area is adjacent to second area without overlapping. First touch signal line is coupled to first touch electrode and second touch electrode. First touch signal line is configured to transmit first touch signal of first area at a first stage. First touch signal line is configured to transmit a common electrode signal at a second stage. First touch signal line is configured to transmit second touch signal of second area at a third stage.
    Type: Application
    Filed: November 29, 2022
    Publication date: November 2, 2023
    Inventors: Che-Min LIN, Chun-Ru HUANG, Chu-Kuan YU, Fang-Ming TSAO, Kai-Teng CHIANG
  • Patent number: 11802262
    Abstract: The present invention provides a system for accelerating the food oxidation rate, comprising a control unit, a baseband circuit, a radio-frequency circuit and an array of antennas. The control unit is used to generate a digital control signal of a spectrum waveform. The baseband and radio-frequency circuits generate analog signal of millimeter-wave according to the control signal of a spectrum waveform. The baseband circuit and the array of antennas emit the analog signal of millimeter-wave toward the food, wherein the analog signal of millimeter-wave has a plurality of first frequency signals and a plurality of second frequency signals, and the first frequency signals and the second frequency signals are alternately arranged and spaced from each other and comprise a plurality of sinusoidal waveforms.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: October 31, 2023
    Assignee: Millitronic Co., Ltd.
    Inventors: Ya-Chung Yu, Chih-Min Lin
  • Publication number: 20230343780
    Abstract: An electrostatic discharge (ESD) protection structure including a P-type substrate, a P-type structure, an N-type buried layer, an element active region, a P-type guard ring, and an N-type structure is provided. The P-type structure is formed in the P-type substrate and serves as an electrical contact of the P-type substrate. The N-type buried layer is formed in the P-type substrate. The element active region is formed on the N-type buried layer. The P-type guard ring is formed on the N-type buried layer and surrounds the element active region. The N-type structure is formed on the N-type buried layer and disposed between the P-type guard ring and the P-type structure.
    Type: Application
    Filed: April 20, 2022
    Publication date: October 26, 2023
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Chang-Min LIN, Chih-Hsuan LIN, Yeh-Ning JOU, Hwa-Chyi CHIOU, Jian-Hsing LEE
  • Publication number: 20230344881
    Abstract: Aspects of the present disclosure involve a system comprising a computer-readable storage medium storing a program and method for communicating with a user external to a virtual conference. The program and method provide, in association with designing a room for virtual conferencing, an interface for configuring an external communication element to communicate with an external user; receive, via the interface, an indication of first user input for setting properties for the external communication element; provide, in association with virtual conferencing for the room, the external communication element in the room based on the properties; receive an indication of second user input selecting the external communication element; and provide, in response to receiving indication of the second user input, for communication with the external user based on the properties.
    Type: Application
    Filed: June 29, 2023
    Publication date: October 26, 2023
    Inventors: Andrew Cheng-min Lin, Walton Lin