Abstract: The present invention provides a wafer structure having a plurality of bonding pad, an adhesion layer, a barrier layer, a wetting layer, a plurality of bump, a first passivation layer and a second passivation layer. The bonding pads are disposed on the active surface of the wafer and exposed by the first passivation layer. The second passivation layer is disposed on the first passivation layer and exposing the bonding pads. An adhesion layer is disposed on the bonding pad and covers a portion of the first passivation layer. The second passivation layer covers the first passivation layer and a portion of the adhesion layer. The barrier layer and the wetting layer are sequentially disposed on the adhesion layer and the bumps are disposed on the wetting layer.

Abstract: A wafer level passive component is directly formed on an active surface of the chip. Conductive patterns and a dielectric pattern are used to form a capacitor and electrically connect to contact pads of the chip. Therefore, the internal wiring of the chip can directly connect to the wafer level passive component disposed on the active surface of the chip, increasing the electrical performance of the chip.

Abstract: An under bump metallurgy structure is applicable to be disposed above the wafer and on the bonding pads of the wafer. The wafer comprises a passivation layer and an under bump metallurgy structure. The passivation layer exposes the bonding pads, and the under bump metallurgy structure including an adhesive layer, a first barrier layer, a wetting layer and a second barrier layer are sequentially formed on the bonding pads. Specifically, the material of the second barrier mainly includes tin-copper alloy.

Abstract: An under bump metallurgy structure is applicable to be disposed above the wafer and on the bonding pads of the wafer. The wafer comprises a passivation layer and an under bump metallurgy structure. The passivation layer exposes the wafer pads, and the under bump metallurgy structure including an adhesive layer, a first barrier layer, a wetting layer and a second barrier layer are sequentially formed on the bonding pads. Specifically, the material of the second barrier mainly includes lead.

Abstract: An under bump metallurgy structure is applicable to be disposed above the wafer and on the bonding pads of the wafer. The wafer comprises a passivation layer and an under bump metallurgy structure. The passivation layer exposes the bonding pads, and the under bump metallurgy structure including an adhesive layer, a first barrier layer, a wetting layer and a second barrier layer are sequentially formed on the bonding pads. Specifically, the material of the second barrier mainly includes tin-nickel alloy.

Abstract: The present invention provides a flip-chip package substrate including a plurality of stacked patterned circuit layers, a plurality of dielectric layers disposed between two neighboring patterned circuit layers and a plurality of bumps. The outmost layers of the patterned circuit layers include a plurality of first contacts and a plurality of second contacts. The bumps are connected to the corresponding first contacts. Since the bumps are formed on the substrate by low-cost implanting or printing apparatuses, the production cost of the flip chip package structure is lowered and the yield of the flip chip package process is improved.

Abstract: A chip structure comprising a chip, a redistribution layer, a second passivation layer and at least a bump is provided. The chip has a first passivation layer and at least a bonding pad. The first passivation layer exposes the bonding pad and has at least a recess. The redistribution layer is formed over the first passivation layer and electrically connected to the bonding pad. Furthermore, the redistribution layer also extends from the bonding pad to the recess. The second passivation layer is formed over the first passivation layer and the redistribution layer. The second passivation layer also has an opening that exposes the redistribution layer above the recess. The bump passes through the opening and connects electrically with the redistribution layer above the recess.

Abstract: A method of forming bumps on the active surface of a silicon wafer. An under-ball metallic layer is formed over the active surface of the wafer. A plurality of first solder blocks is attached to the upper surface of the under-ball metallic layer. Each first solder block has an upper surface and a lower surface. The lower surface of each first solder block bonds with the under-ball metallic layer. The upper surfaces of the first solder blocks are planarized. A second solder block is attached to the upper surface of each first solder block and then a reflow operation is carried out.

Abstract: The present invention provides a method for treating the wafer surface, suitable for removing residues on the wafer surface. The method includes forming a photo-sensitive material layer over the wafer surface covering the bumps and the under bump metallurgy layer on the wafer surface. Using the bumps as masks, the photo-sensitive material layer is exposed and developed, to expose the wafer surface between the bumps. A wet etching process is then performed to remove residues on the exposed wafer surface and then the remained photo-sensitive material layer is removed. Therefore, no residues remain on the wafer surface, and the yield of the bumps is increased.

Abstract: A method of forming a plurality of bumps over a wafer mainly comprises providing the wafer having a plurality of bonding pads formed thereon, forming an under bump metallurgy (UBM) layer over the bonding pads wherein the UBM layer includes an adhesive layer, for example a titanium (Ti) layer or an aluminum (Al) layer, and at least one electrically conductive layer formed on the adhesive layer, removing the portions of the electrically conductive layer located outside the bonding pads, forming a plurality of bumps over the residual portions of the electrically conductive layer disposed above the bonding pads, etching the adhesive layer located outside the bumps, and then reflowing the bumps.

Abstract: A method of forming a plurality of bumps over a wafer. The wafer has an active surface having a passivation layer and a plurality of contact pads thereon. The passivation layer exposes the contact pads on the active surface. An adhesion layer is formed over the active surface of the wafer and covers both the contact pads and the passivation layer. A metallic layer is formed over the adhesion layer. The adhesion layer and the metallic layer are patterned so that the adhesion layer and the metallic layer remain on top of the contact pads. A photoresist layer is formed on the active surface of the wafer. The photoresist layer has a plurality of openings that expose the metallic layer. Flux material is deposited into the openings and then a solder block is disposed into each of the openings. A reflow process is carried out so that the solder block bonds with the metallic layer. Finally, the flux material and the photoresist layer are removed.

Abstract: The present invention relates to an under bump metallurgy layer, comprising an adhesion layer, a barrier layer and a wetting-barrier layer. The adhesion layer, the barrier layer and the wetting-barrier layer are arranged sequentially on the pad of the chip, and the wetting-barrier layer is disposed between the barrier layer and the bump. The wetting-barrier layer, containing nickel, can improve the bonding ability between the pad and the bump. Also, the invention relates to a flip chip structure including at least a chip, a plurality of bumps and the under bump metallurgy mentioned above.

Abstract: A wafer bumping process is disclosed. A wafer having a plurality of bonding pads formed thereon is provided. A first under bump metallurgy layer is formed to cover the bonding pads. A first patterned photoresist layer having a plurality of first openings is formed on the first under bump metallurgy layer, wherein a portion of the first under bump metallurgy layer is exposed within the first openings. A second under bump metallurgy layer is formed within the first openings, wherein the second under bump metallurgy layer is much thicker than the first under bump metallurgy layer. A second patterned photoresist layer having a plurality of second openings is formed on the first patterned photoresist layer, wherein the second openings being larger than the first openings.

Abstract: A method of assembling a passive component over the active surface of a die is provided. The method shortens the signal transmission path between the die and the passive component so that electrical performance of the die after packaging is improved. In addition, the transmission path and the number of contacts on the substrate for connecting the die and the passive component are reduced. With a reduction in transmission path, size of the substrate can be reduced. Furthermore, a plurality of passive components may be assembled onto the dies of a wafer in a single operation so that there is no need to assemble individual passive component over each packaging substrate.

Abstract: A method for preventing burnt fuse pads from further electrical connection suitable before the formation of bumps on the wafer. A dielectric layer is formed over the active surface of the wafer covering the bump pads and the fuse pads of the wafer, wherein a central region of the fuse pads is burnt to form a gap which allows the material of the dielectric layer to fill up the gap. Afterwards, either a part of the dielectric layer is removed and the part of the dielectric layer covering the fuse pads remainsor a part of the dielectric layer covering the bump pads is removed. Then, an under ball metallurgy layer is formed on the bump pads of the wafer so that the material of the under ball metallurgy layer does not cover the two sides of the fuse pad at the same time, or fill into the gap. As a result, the electrical isolation still remains.

Abstract: A solder ball fabricating process for forming solder balls over a wafer having an active layer is provided. A patterned solder mask layer is formed over the active surface of the wafer. The patterned solder mask layer has an opening that exposes a bonding pad on the wafer. Solder material is deposited into the opening over the bonding pad. A reflow process is conducted to form a pre-solder body. The aforementioned steps are repeated so that various solder materials are fused together to form a solder ball over the bonding pad.

Abstract: A semiconductor device with a capability can prevent a burnt fuse pad from re-electrical connection, wherein the semiconductor device includes a bump pad and a fuse pad over a wafer. The fuse pad includes the burnt fuse pad having a gap for electrical isolation. The semiconductor device comprises a dielectric layer, disposed substantially above the burnt fuse pad and filling the gap, and a bump structure, disposed on the bump pad. The foregoing semiconductor device can further comprise a passivation layer, which exposes the bump pad and a portion of the burnt fuse pad. Wherein, the dielectric layer is over the passivation layer, covers the exposed portion of the burnt fuse pad and fills the gap.

Abstract: A method for making UBM (Under Bump Metallurgy) pads and bumps on a wafer is disclosed. Openings are formed in a photoresist layer for forming bumps, a positive liquid photoresist is provided into the openings of the photoresist layer for forming bumps. The positive liquid photoresist is exposed and developed to modify the openings of the photoresist layer. Thus, bumps formed in the modified openings have precise bonding areas on the UBM layer. Using the bumps as a mask, UBM pads under the bumps are formed by etching the UBM layer, so that the reflowed bumps have an uniform height.

Abstract: The present invention provides a bump fabrication process. A wafer is provided with a patterned photoresist layer formed on the wafer. The patterned photoresist layer has a plurality of openings, corresponding to bonding pads. A conductive layer is formed on the photoresist layer and the exposed bonding pads. Afterwards, a sticker film is the provided to lift off the conductive layer on the photoresist layer, while the conductive layer within the openings is not removed. A solder paste is filled into the openings. A reflow step is performed to turn the filled solder paste into globular bumps. At last, the protoresist layer is removed.

Abstract: A solder ball attaching process for attaching solder balls to a wafer is provided. First, an under-ball-metallurgy layer is formed on the active surface of the wafer. Patterned masking layers are sequentially formed over the active surface of the wafer. The masking layers together form a step opening structure that exposes the under-ball-metallic layer. A solder ball is placed on the uppermost masking layer and allowed to roll so that the solder ball drops into the step opening structure by gravity. A reflow process is conducted to join the solder ball and the under-ball-metallurgy layer together. Finally, various masking layers are removed to expose the solder ball on the bonding pad of the wafer.