Abstract: A method for forming bumps is disclosed. First, a substrate having an under bump metallurgy (UBM) layer thereon is provided. Next, a patterned photoresist is disposed over the surface of the UBM layer, in which an opening is formed within the photoresist to expose part of the UBM layer. Next, a foot plating is disposed into the opening to partially cover the UBM layer and a solder is deposited into the opening thereafter. After removing the photoresist, an etching process is performed to remove part of the foot plating and the UBM layer by utilizing the solder as a mask. A reflow process is performed thereafter to transform the solder into a bump.

Abstract: The present invention provides a method for treating the wafer surface, suitable for removing residues on the wafer surface. The method includes forming a photo-sensitive material layer over the wafer surface covering the bumps and the under bump metallurgy layer on the wafer surface. Using the bumps as masks, the photo-sensitive material layer is exposed and developed, to expose the wafer surface between the bumps. A wet etching process is then performed to remove residues on the exposed wafer surface and then the remained photo-sensitive material layer is removed. Therefore, no residues remain on the wafer surface, and the yield of the bumps is increased.

Abstract: A method for utilizing a dry film is provided. A dry film is pressed onto a substrate, such as a wafer. The dry film includes a photoresist layer tightly attached to the substrate and an exposed carrier film with light transmission. Before exposure and development, the carrier film of the dry film is cleaned in a darkroom, wherein the cleaning method may include a step of chemical spraying and a step of rinsing through DI water. Accordingly, the contaminant on the carrier film can be removed. In addition, the dry film burrs can be also removed. Thus, an excellent production yield for sequent exposure and development can be achieved.

Abstract: A wafer-level package structure, applicable to a flip-chip arrangement on a carrier, which comprises a plurality of contact points, is described. This wafer-level package structure is mainly formed with a chip and a conductive layer. The conductive layer is arranged on the bonding pads of the chip as contact points. The conductive layer can further be arranged at a region outside the bonding pads on the chip as a heat sink to enhance the heat dissipation ability of the package.

Abstract: A chip structure can reduce the phenomenon of overcrowding current at the conventional circular opening of the passivation layer and further causing electromigration when the current flows to the bonding pad via the transmission line. The improved structure for the side profile of the opening of the passivation layer is about a circular profile, but the portion near to the transmission line is a straight line or a curving line. When the current flows through this opening, the current density can be uniformly distributed along the straight line or the curving line, and whereby the phenomenon of overcrowding current can be reduced.

Abstract: A bumping process is provided. The bumping process comprises the steps of: firstly, providing a wafer; next forming an under bump metallurgy (UBM) on the active surface of the wafer; then, forming a photo-resist layer on the active surface of the wafer and forming at least an opening in the photo-resist layer; then, sequentially forming a copper post, a barrier and a copper layer; then removing the photo-resist layer; finally reflowing the solder layer in the opening. The barrier layer is made of the materials such as nickel, lest the copper post and the solder layer might contact directly, causing the copper to diffuse fast and lose accordingly. Therefore, the quality of bumping process and structure can be enhanced according to the present invention.

Abstract: A bumping process is provided as following: at first, providing a wafer, then forming a first photo-resist layer on a active surface of the wafer and forming at least a first opening on the first photo-resist layer; and forming a copper pillar in the first opening; then forming a second photo-resist layer on the first photo-resist layer and forming at least a second opening on the second photo-resist layer; finally forming a solder layer in the second opening to attach the solder layer on the copper pillar, and removing the first and second photo-resist layer.

Abstract: A bumping process includes the steps of: firstly, providing a wafer; forming a first photo-resist layer on a active surface of the wafer and forming at least a first opening on the first photo-resist layer; next, forming a first copper pillar in the first opening; next, forming a second photo-resist layer on the first photo-resist layer and forming at least a second opening on the second photo-resist layer, wherein the second opening smaller than the first opening so that a portion of the surface of the first copper pillar is exposed in the second opening; then, forming a second copper pillar in the second opening; finally, forming a solder layer on the second copper pillar; and removing the first and second photo-resist layers.

Abstract: A bumping process is provided as following: at first, providing a wafer, then forming a first photo-resist layer on a active surface of the wafer and forming at least a first opening on the first photo-resist layer; and forming a first copper pillar in the first opening; then forming a second photo-resist layer on the first photo-resist layer and forming at least a second opening on the second photo-resist layer, wherein the second opening is bigger than the first opening so that the first copper pillar and the surrounding first photo-resist layer are exposed in the second opening; and forming a second copper pillar in the second opening; finally forming a solder layer onto the second pillar, and removing the first and second photo-resist layers.

Abstract: A chip scale package with micro antenna includes a chip, a first dielectric layer and an antenna. The chip has an active surface, a first bonding pad and a second bonding pad on the active surface. The first dielectric layer is formed on the active surface of the chip. The first dielectric layer has a plurality of openings to expose the first bonding pad and the second bonding pad. Each of the openings has an expanding inclined sidewall. The antenna is formed on the upper surface of the first dielectric layer and connected to the first bonding pad and the second bonding pad through the inclined sidewall of the openings for preventing antenna cracking.

Abstract: An under bump metallurgic (UBM) layer which is adapted for a chip is disclosed. The UMM layer alleviate the loss of electromigration resulting from current crowing effect at the corner of UBM layer near the transmission line. By increasing the thickness of the UBM layer at the particular region which is close to the transmission line, losses of the UBM layer due to electromigration can be compensated. The life time of the chip is, therefore, enhanced.

Abstract: A wafer comprises a wafer, a conductor, a first passivation layer, a second passivation layer, a redistribution layer, and a third passivation layer. The conductor is disposed on the wafer. The first passivation layer covers the wafer, and exposes the surface of the conductor. The second passivation layer having an aperture is formed on the first passivation layer, and the aperture relatively to a pre-designed line exposes the surface of the conductor. The redistribution layer comprising a first and second metallic layer is formed in the aperture. The first metallic layer is disposed in the aperture. The second metallic layer peripherally covers the first metallic layer, and is connected to the inner wall of the aperture formed by the first passivation layer, second passivation layer and the conductor. The third passivation layer is formed on the second passivation layer and the first metallic layer of the redistribution layer.

Abstract: A method for making UBM (Under Bump Metallurgy) pads and bumps on a wafer is disclosed. Openings are formed in a photoresist layer for forming bumps, a positive liquid photoresist is provided into the openings of the photoresist layer for forming bumps. The positive liquid photoresist is exposed and developed to modify the openings of the photoresist layer. Thus, bumps formed in the modified openings have precise bonding areas on the UBM layer. Using the bumps as a mask, UBM pads under the bumps are formed by etching the UBM layer, so that the reflowed bumps have a uniform height.

Abstract: The present invention relates to a method for forming a redistribution layer in a wafer structure. The method comprises: (a) providing a wafer having a plurality of conductive structures and a first passivation layer thereon, wherein the first passivation layer covers the wafer except the conductive surfaces of the conductive structures; (b) forming a second passivation layer over the first passivation layer; (c) selectively removing part of the second passivation layer to form a plurality of grooves corresponding to a predetermined circuit; (d) forming a redistribution layer in the grooves; and (e) forming a third passivation layer over the second passivation layer and the redistribution layer. As a result, the redistribution layer is “embedded” in the second passivation layer so as to avoid the delamination of the redistribution layer.

Abstract: A method and structure for a conductive bump are provided herein. A conductive surface is provided on a wafer. A conductive barrier layer and a conductive wetting layer on a part of the conductive surface have a bottom and a side wall and further reach up a top surface. The conductive wetting and barrier layers constitute inside and outside side walls, respectively. A conductive seed layer covers the conductive wetting layer and the top surface. Another conductive barrier and conductive bump are subsequently formed on the conductive seed layer.

Abstract: A method of forming bumps on the active surface of a silicon wafer. A first under-bump metallic layer is formed over the active surface of the wafer. A second under-bump metallic layer is formed over the first under-bump metallic layer. A portion of the second under-bump metallic layer is removed to expose the first under-bump metallic layer. A plurality of solder bumps is implanted onto the second under-bump metallic layer. The exposed first under-bump metallic layer is removed so that only the first under-bump metallic layer underneath the second under-bump metallic layer remains.

Abstract: A screen printing method of conductive material is applied to a wafer with a conductive surface thereon. A dielectric layer on the wafer exposes the conductive surface to a first opening. A mask formed on the dielectric layer has a plurality of second openings corresponding to the first opening. The conductive surface is exposed by the second openings. The conductive surface is covered with a conductive material that flows into the first opening through the second openings. Then the mask is removed. With the arrangement and dimension control of the second openings, the conductive material easily flows into the first opening and is not over-scraped.

Abstract: A bump fabrication process for forming a bump over a wafer having a plurality of bonding pads thereon is provided. A patterned solder mask layer having a plurality of openings that exposes the respective bonding pads is formed over a wafer. The area of the opening in a the cross-sectional area through a the bottom-section as well as through a the top-section of the opening is smaller than the area of the opening in a the cross-sectional area through a the mid-section of the opening. Solder material is deposited into the opening and then a reflow process is conducted fusing the solder material together to form a spherical bump inside the opening. Finally, the solder mask layer is removed. In addition, a pre-formed bump may form on the bonding pad of the wafer prior to forming the patterned solder mask layer over the wafer having at least with an opening that exposes the pre-formed bump.

Abstract: A semiconductor chip with bumps formed therein comprises an active surface, a plurality of bonding pads, a passivation layer, a plurality of first UBMs (under bump metallurgy), a second UBM, a plurality of first bumps, and a plurality of second bumps. The bonding pads are disposed on the active surface of the semiconductor chip. The passivation layer covers the active surface of the semiconductor chip with the pads exposed out of the passivation layer. The first UMBs are individually disposed on the bonding pads. The second UMB is disposed on at least two of the bonding pads. The first bumps are disposed on the first UMBs. The second bumps are disposed on the second UBM.

Abstract: A method for forming a photoresist layer on a substrate to improve the joining of the photoresist layer and the substrate is provided. For a bumping process using the method, a liquid is used to react with the photoresist layer to form a combination layer of good fluidity between the photoresist layer and the passivation layer on the substrate. The combination layer fills the pits of the passivation layer to improve the joining of the photoresist layer and the passivation layer. Therefore, when the solder material is filled into the openings, no solder material stays between the photoresist layer and the passivation layer, so as to avoid solder bridging between the two adjacent pads.