Patents by Inventor Min Shen

Min Shen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11194812
    Abstract: The disclosed embodiments provide a system for processing data. During operation, the system organizes fact data to be aggregated into sliding time window features and observation data associated with the fact data into a set of partitions based on a join key. Next, the system sorts the fact data and the observation data within the set of partitions by the join key and timestamps associated with the fact data and the observation data. For each observation record in the observation data, the system aggregates fact records in the sorted fact data that share a value of the join key with the observation record and that fall within a first time window associated with the observation record to produce a sliding time window feature. The system then stores the sliding time window feature in association with the observation record.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: December 7, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Min Shen, Maneesh Varshney, David J. Stein, Jian Qiao
  • Publication number: 20210375345
    Abstract: A memory circuit includes a memory array including a plurality of memory cells, each memory cell including a gate structure including a ferroelectric layer and a channel layer adjacent to the gate structure, the channel layer including a metal oxide material. A driver circuit is configured to output a gate voltage to the gate structure of a memory cell, the gate voltage having a positive polarity and a first magnitude in in a first write operation and a negative polarity and a second magnitude in in a second write operation, and to control the second magnitude to be greater than the first magnitude.
    Type: Application
    Filed: March 11, 2021
    Publication date: December 2, 2021
    Inventors: Huan-Sheng WEI, Tzer-Min SHEN, Zhiqiang WU
  • Publication number: 20210327844
    Abstract: A semiconductor package includes a first chip and a second chip arranged side by side on a carrier substrate. The first chip is provided with a high-speed signal pads along a first side in proximity to the second chip. The second chip includes a redistribution layer, and the redistribution layer is provided with data (DQ) pads along the second side in proximity to the first chip. A plurality of first bonding wires is provided to directly connect the high-speed signal pads to the DQ pads. The redistribution layer of the second chip is provided with first command/address (CA) pads along the third side opposite to the second side, and a plurality of dummy pads corresponding to the first CA pads. The plurality of dummy pads are connected to second CA pads disposed along a fourth side of the second chip via interconnects of the redistribution layer.
    Type: Application
    Filed: March 5, 2021
    Publication date: October 21, 2021
    Inventors: Chin-Yuan Lo, Chih-Hao Chang, Tze-Min Shen
  • Publication number: 20210308928
    Abstract: A honeycomb extrusion die (120) includes a die body (302) including an inlet face (306) and an exit face. The die body (302) has slot inlets (309) and a plurality of pins (320, 500) disposed between the slot inlets (309) and the exit face. The plurality of pins (320, 500) include side surfaces (322, 500B) configured to define a matrix of intersecting slots (324), wherein the matrix of intersecting slots (324) has slot exit (509) widths at the exit face. Divots (526) extend into a plurality of the side surfaces (322, 500B) between the slot inlets (309) and the exit face. Each individual divot (526) has a divot san depth (D55) extending into a side surface (500A, 500B, 502A, 502B) of the side surfaces (322, 500B). A ratio between a slot exit width (W53) W53 of an individual slot (324) and the divot depth (D55) of an individual divot (526) extending into a side surface (500A, 500B, 502A, 502B) of the individual slot (324) is greater than 1.2.
    Type: Application
    Filed: May 30, 2019
    Publication date: October 7, 2021
    Inventors: Thomas William Brew, Yuehao Li, Min Shen
  • Publication number: 20210305372
    Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a channel member including a first channel layer and a second channel layer over the first channel layer, and a gate structure over the channel member. The first channel layer includes silicon, germanium, a III-V semiconductor, or a II-VI semiconductor and the second channel layer includes a two-dimensional material.
    Type: Application
    Filed: July 23, 2020
    Publication date: September 30, 2021
    Inventors: Mrunal Abhijith Khaderbad, Dhanyakumar Mahaveer Sathaiya, Keng-Chu Lin, Tzer-Min Shen
  • Patent number: 11129835
    Abstract: The invention features compositions and methods for inhibiting the Pin1 protein, and the treatment of disorders characterized by elevated Pin1 levels.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: September 28, 2021
    Assignees: Beth Israel Deaconess Medical Center, Inc., The United States of America, as represented by the Secretary, Department of Health and Human Services Office of Technology Transfer, National Institutes of Health
    Inventors: Kun Ping Lu, Matthew Brian Boxer, Mindy Irene Emily Davis, Rajan Pragani, Min Shen, Anton Momtchilov Simeonov, Shuo Wei, Xiao Zhen Zhou
  • Publication number: 20210296485
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first fin active region of a first semiconductor material disposed within the first region, oriented in a first direction, wherein the first fin active region has a <100> crystalline direction along the first direction; and a second fin active region of a second semiconductor material disposed within the second region and oriented in the first direction, wherein the second fin active region has a <110> crystalline direction along the first direction.
    Type: Application
    Filed: June 7, 2021
    Publication date: September 23, 2021
    Inventors: Tzer-Min Shen, Zhiqiang Wu, Chung-Cheng Wu, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang, Min Cao
  • Publication number: 20210260535
    Abstract: The invention belongs to the technical field of composite membrane, and in particular discloses a UIO-66-NH2 doped organosilicon high salinity wastewater treatment membrane and a preparation method thereof. The membrane is formed into UIO-66-NH2/organosilicon hybrid membrane on the prefabricated ceramic support surface through the dip-coating method by doping the UIO-66-NH2 metal-organic framework material into the organosilicon polymeric sol. The UIO-66-NH2/organosilicon hybrid membrane prepared by the present invention exhibits high water permeability (up to 1.6×10?10 m3/(m2 s Pa) and high salt retention (NaCl retention rate is more than 99.9.%) in the application of pervaporation desalination, and maintains stable membrane structure in the treatment process of TDS>5 wt % high salinity wastewater.
    Type: Application
    Filed: February 3, 2021
    Publication date: August 26, 2021
    Inventors: Rong XU, Qian LIU, Chunhui ZHU, Jing ZHONG, Xiuxiu REN, Min SHEN, Yihan ZHANG
  • Patent number: 11045975
    Abstract: A honeycomb extrusion die comprising at least some slots (308) each with a divot (312) spaced toward a discharge surface (324) from a feedhole-slot intersection (332) and a wide portion at the discharge surface extending into the die body (358) to the divot (312) to strengthen a peripheral region of a honeycomb extrudate in a reinforcement region, and a bulk nominal section corresponding to a bulk region of the honeycomb body.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: June 29, 2021
    Assignee: Corning Incorporated
    Inventors: John Wilbur Allard, Thomas William Brew, Tushar Gulati, Helmut Roland Letzel, Min Shen
  • Patent number: 11031418
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first fin active region of a first semiconductor material disposed within the first region, oriented in a first direction, wherein the first fin active region has a <100> crystalline direction along the first direction; and a second fin active region of a second semiconductor material disposed within the second region and oriented in the first direction, wherein the second fin active region has a <110> crystalline direction along the first direction.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: June 8, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tzer-Min Shen, Zhiqiang Wu, Chung-Cheng Wu, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang, Min Cao
  • Publication number: 20210147571
    Abstract: The invention relates to the field of biomedicine. In particular, the invention relates to an isolated monoclonal antibody or antigen-binding fragment thereof against human tumor stem cells, and the use of said antibody or fragment in the treatment and diagnosis of tumors.
    Type: Application
    Filed: March 21, 2018
    Publication date: May 20, 2021
    Applicant: Suzhou Bojuhua Biomedical Technology Co. Ltd
    Inventor: Min Shen
  • Publication number: 20210130242
    Abstract: A coated ceramic honeycomb body comprising a honeycomb structure comprising a matrix of intersecting porous walls forming a plurality of axially-extending channels, at least some of the plurality of axially-extending channels being plugged to form inlet channels and outlet channels, wherein a total surface area of the outlet channels is greater than a total surface area of the inlet channels, and wherein a catalyst is preferentially located within the outlet channels, and preferentially disposed on non-filtration walls of the outlet channels. Methods and apparatus configured to preferentially apply a catalyst-containing slurry to the outlet channels and non-filtration walls are provided, as are other aspects.
    Type: Application
    Filed: May 3, 2019
    Publication date: May 6, 2021
    Inventors: Douglas Munroe Beall, Achim Karl-Erich Heibel, Konstantin Vladimirovich Khodosevich, Kenneth Richard Miller, Hrushikesh Govindrao Pimpalgaonkar, Kunal Upendra Sakekar, Min Shen, Todd Parrish St Clair
  • Publication number: 20210075741
    Abstract: Systems and methods for allocating resources. The system includes a communications module, a processor, and a memory. The memory stores a data record and instructions that, when executed, configure the processor to obtain a data record and transmit an existing score indication corresponding to the data record for display at the client device; receive a first time parameter and an action indicator associated with a shared resource and, in response, determine a first provisional score corresponding to the data record based on the existing score indication, the action indicator, and the first time parameter to provide a first provisional score indication; transmit the first provisional score indication and a selectable option associated with the action indicator for display at the client device while the first provisional score indication is displayed; and in response to receiving a resource transfer instruction, allocate the shared resource associated with the action indicator.
    Type: Application
    Filed: November 20, 2020
    Publication date: March 11, 2021
    Applicant: The Toronto-Dominion Bank
    Inventors: Peter HORVATH, Gregory Richard HARPER, Richard THOMAS, Tricia Elizabeth ALLEN, Joe MOGHAIZEL, Aline da Rosa ALVES, Lawrence Anthony ALLEN, Kimberly Elizabeth LAM, Min SHEN, Melanie Judith MENDOZA, Vanessa LI, Alexandra ANTONUCCI, Audrey Madeleine CARR
  • Patent number: 10879238
    Abstract: Devices and methods of forming a FET including a substrate having a first fin and a second fin extending therefrom. A high-k gate dielectric layer and a ferroelectric insulator layer are deposited over the first fin and the second fin. In some embodiments, a dummy gate layer is deposited over the ferroelectric insulator layer over the first fin and the second fin to form a first gate stack over the first fin and a second gate stack over the second fin. The dummy gate layer of the first gate stack is then removed (while maintaining the ferroelectric insulator layer) to form a first trench. And the dummy gate layer and the ferroelectric insulator layer of the second gate stack are removed to form a second trench. At least one metal gate layer is formed in the first trench and the second trench.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng Ching, Kuan-Lun Cheng, Chih-Hao Wang, Sai-Hooi Yeong, Tzer-Min Shen, Chi-Hsing Hsu
  • Patent number: 10873542
    Abstract: Systems and methods for allocating resources. The system includes a communications module, a processor, and a memory. The memory stores a data record and instructions that, when executed, configure the processor to obtain a data record and transmit an existing score indication corresponding to the data record for display at the client device; receive a first time parameter and an action indicator associated with a shared resource and, in response, determine a first provisional score corresponding to the data record based on the existing score indication, the action indicator, and the first time parameter to provide a first provisional score indication; transmit the first provisional score indication and a selectable option associated with the action indicator for display at the client device while the first provisional score indication is displayed; and in response to receiving a resource transfer instruction, allocate the shared resource associated with the action indicator.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: December 22, 2020
    Assignee: The Toronto-Dominion Bank
    Inventors: Peter Horvath, Gregory Richard Harper, Richard Thomas, Tricia Elizabeth Allen, Joe Moghaizel, Aline da Rosa Alves, Lawrence Anthony Allen, Kimberly Elizabeth Lam, Min Shen, Melanie Judith Mendoza, Vanessa Li, Alexandra Antonucci, Audrey Madeleine Carr
  • Patent number: 10861972
    Abstract: The demand for increased performance and shrinking geometry from ICs has brought the introduction of multi-gate devices including finFET devices. Inducing a higher tensile strain/stress in a region provides for enhanced electron mobility, which may improve performance. High temperature processes during device fabrication tend to relax the stress on these strain inducing layers. In some embodiments, the present disclosure relates to a finFET device and its formation. A strain-inducing layer is disposed on a semiconductor fin between a channel region and a metal gate electrode. First and second inner spacers are disposed on a top surface of the strain-inducing layer and have inner sidewalls disposed along outer sidewalls of the metal gate electrode. First and second outer spacers have innermost sidewalls disposed along outer sidewalls of the first and second inner spacers, respectively. The first and second outer spacers cover outer sidewalls of the first and second inner spacers.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Zhiqiang Wu, Yi-Ming Sheu, Tzer-Min Shen, Chun-Fu Cheng, Hong-Shen Chen
  • Patent number: 10848099
    Abstract: A power generation abnormality detection method includes operating a power converter to controllably operate a solar cell module at a plurality of predetermined voltage points to obtain a plurality of measured currents, utilizing the predetermined voltage points and measured currents to calculate a plurality of first power data, comparing the plurality of first power data with a first PV curve, or operating the power converter to controllably operate the solar cell module at a plurality of predetermined current points to obtain a plurality of measured voltages, utilizing the predetermined current points and measured voltages to calculate a plurality of second power data, and comparing the plurality of second power data with a second PV curve.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: November 24, 2020
    Assignee: ABLEREX ELECTRONICS CO., LTD.
    Inventors: Yao-Jen Chang, Chia-Hung Lee, Jia-Min Shen, Yu-Hsiu Lin
  • Patent number: 10836759
    Abstract: A compound of Formula II or a pharmaceutically acceptable salt thereof, wherein CyN is a cyclic amine group bound via a nitrogen atom; X is C or N; R1 and R2 are each independently a halogen, CN, CF3, CHF2, CH2F, a C1-C10alkyl group, a C1-C10alkoxy group, a di(C1-C5alkyl)amino; m and n are each independently 1, 2, or 3, and represents either a single bond or a double bond, wherein the racemic mixture of 3-(4-(4-chlorophenyl)thiazol-2-yl)-1-(2-ethyl-5-methoxyphenyl)-6-(2-methylprop-1-en-1-yl)-5-(piperazine-1-carbonyl)pyridin-2(1H)-one atropisomers is excluded.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: November 17, 2020
    Assignees: THE UNIVERSITY OF NORTH CAROLINA AT CHAPEL HILL, THE UNITED STATES OF AMERICA, AS REPRESENTED BY THE SECRETARY, DEPARTMENT OF HEALTH AND HUMAN SERVICES
    Inventors: Matthew Brian Boxer, Xiaodong Wang, Kyle Ryan Brimacombe, Mindy Irene Emily Davis, Yuhong Fang, Matthew Hall, Ajit Jadhav, Surendra Karavadhi, Li Liu, Natalia Martinez, Andrew Louis McIver, Rajan Pragani, Jason Matthew Rohde, Anton Simeonov, Wei Zhao, Min Shen
  • Patent number: RE48304
    Abstract: A device includes a semiconductor fin over a substrate, a gate dielectric on sidewalls of the semiconductor fin, and a gate electrode over the gate dielectric. A source/drain region is on a side of the gate electrode. A dislocation plane is in the source/drain region.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: November 10, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zhiqiang Wu, Wen-Hsing Hsieh, Hua Feng Chen, Ting-Yun Wu, Carlos H. Diaz, Ya-Yun Cheng, Tzer-Min Shen
  • Patent number: D931052
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: September 21, 2021
    Inventor: Min Shen