Abstract: An integrated circuit device includes a stack of integrated circuit memory dies having a plurality of through-substrate vias (TSVs) extending therethrough, and a buffer die electrically coupled to the plurality of TSVs. The buffer die includes a test interface circuit, which is configured to: (i) generate a plurality of internal test signals, which are synchronized with a second clock signal having a second frequency, from at least one control code, and from a plurality of external test signals, which are synchronized with a first clock signal having a first frequency less than the second frequency, and (ii) provide the plurality of internal test signals to at least one of the memory dies in said stack during a first test mode. The second frequency may be greater than three (3) times the first frequency.

Abstract: A spatial disturbance that occurs when an access is concentrated in a specific memory area in a volatile semiconductor memory like DRAM is properly solved by a memory controller. The memory controller includes a concentration access detection part generating a concentration access detection signal when an address for accessing a specific memory area among memory areas of volatile semiconductor memory is concentratedly received. In the case that the concentration access detection signal is generated, the memory controller includes a controller for easing or preventing corruption of data which memory cells of the specific memory area and/or memory cells of memory areas adjacent to the specific memory area hold.

Abstract: The present invention relates to a method for purifying polyalkylene carbonate. More specifically, a method for purifying polyalkylene carbonate is provided, which uses a multistage extraction column having the number of stages of at least 10 stages, using water for effectively removing by-products such as alkylene carbonate generated in a process for producing polyalkylene carbonate resin, thereby controlling the content of by-products to a certain level or less through a continuous operation, particularly, the extraction is performed at room temperature, thereby easily removing by-products in the resin without a high temperature volatilization.

Abstract: Semiconductor memory device includes a memory cell array and an interface circuit including an ECC engine. The memory cell array includes a normal cell region and a parity cell region including a first sub parity region and a second sub parity region. The interface circuit receives main data and sub data comprising external parity or a data mask signal, generates a flag signal based on mask bits of the data mask signal, performs ECC encoding operation on the main data in response to an operation mode and the flag signal, stores the main data in the normal cell region, stores either the external parity or the flag signal in the second sub parity region in response to the operation mode, performs an ECC decoding operation on the main data read from the normal cell region in response to the operation mode and the flag signal.

Abstract: The present disclosure relates to an economical method of preparing a resin composition including a polyalkylene carbonate with improved thermal stability and processability. More specifically, the method of preparing a resin composition includes the steps of polymerizing carbon dioxide and an epoxide compound in the presence of a zinc-based catalyst and a solvent, recovering monomers, removing the catalyst and recovering raw materials, solution-blending with a thermostable resin to improve the thermal stability and processability, and removing the solvent and byproducts from the reaction mixture by using an agitated flash drum and an extrusion or kneader-type devolatilizer.

Abstract: A semiconductor memory device which includes a memory cell array, an error injection register set, a data input buffer, a write data generator, and control logic. The error injection register set stores an error bit set, including at least one error bit, based on a first command. The error bit set is associated with a data set to be written in the memory cell array. The data input buffer stores the data set to be written in the memory cell array based on a second command. The write data generator generates a write data set to be written in the memory cell array based on the data set and the error bit set. The control logic controls the error injection register set and the data input buffer.

Abstract: Systems and methods for simultaneous radio frequency (“RF”) transmission and reception for nuclear magnetic resonance applications, such as magnetic resonance imaging (“MRI”) are described. The system includes a simultaneous transmit and receive (“STAR”) control system that compensates for the effects of load changes in a radio frequency (“RF”) coil due to the inevitable motion of living subjects (e.g., from subject motion, respiration, swallowing). The system also maintains a high transmit-receive isolation, even when scanning a subject using a continuous RF broad band sweep excitation.

Abstract: The present invention relates to a super absorbent polymer which not only has excellent basic absorption performance but also can improve rewet characteristics and leakage suppression characteristics of hygienic materials such as diapers, and a method for preparing the same. The super absorbent polymer includes: a base polymer powder including a first cross-linked polymer of a water-soluble ethylenically unsaturated monomer having an acidic group of which at least a part is neutralized; and a surface crosslinked layer that is formed on the base polymer powder and includes a second cross-linked polymer in which the first crosslinked polymer is further crosslinked via a surface crosslinking agent, wherein the surface crosslinking agent includes a mixture of plural kinds of cyclic alkylene carbonates, and where the mixture has a Hansen solubility parameter by hydrogen bonding component of 13 or more.

Abstract: An integrated circuit device includes a stack of integrated circuit memory dies having a plurality of through-substrate vias (TSVs) extending therethrough, and a buffer die electrically coupled to the plurality of TSVs. The buffer die includes a test interface circuit, which is configured to: (i) generate a plurality of internal test signals, which are synchronized with a second clock signal having a second frequency, from at least one control code, and from a plurality of external test signals, which are synchronized with a first clock signal having a first frequency less than the second frequency, and (ii) provide the plurality of internal test signals to at least one of the memory dies in said stack during a first test mode. The second frequency may be greater than three (3) times the first frequency.

Abstract: A cooling/warming device according to one embodiment of the present invention provides a cooling/warming device including a case including a lower case and an upper case coupled to the lower case, a fan which is accommodated in the case and circulates air introduced into the case, a thermoelectric device which is accommodated in the case, is disposed on a side surface of the fan, cools some air generated by the fan, and heats the remaining air, and a controller which is connected to the thermoelectric device and the fan and controls operation of the thermoelectric device and the fan. The thermoelectric device includes a first heat transmission member disposed at a side of the lower case, a second heat transmission member disposed at a side of the upper case, and a thermoelectric element disposed between the first heat transmission member and the second heat transmission member.

Abstract: A device, system, and/or method includes an internal circuit configured to perform at least one function, an input-output terminal set and a repair circuit. The input-output terminal set includes a plurality of normal input-output terminals connected to an external device via a plurality of normal signal paths and at least one repair input-output terminal selectively connected to the external device via at least one repair signal path. The repair circuit repairs at least one failed signal path included in the normal signal paths based on a mode signal and fail information signal, where the mode signal represents whether to use the repair signal path and the fail information signal represents fail information on the normal signal paths. Using the repair circuit, various systems adopting different repair schemes may be repaired and cost of designing and manufacturing the various systems may be reduced.

Abstract: A memory device can include a plurality of memory banks coupled to an input/output bus and a memory controller coupled to the plurality of memory banks. The memory controller can be configured to control operations of the plurality of memory banks, where each of the plurality of memory banks can include a bank array including a plurality of memory cells configured to store data, a latch circuit coupled to the input/output bus, where the latch circuit can be configured to store target data received via the input/output bus to provide stored target data, and a comparison circuit coupled to the latch circuit, where the comparison circuit can be configured to compare stored data output by the bank array with the stored target data to provide result data to the memory controller.

Abstract: Semiconductor memory device includes a memory cell array and an interface circuit including an ECC engine. The memory cell array includes a normal cell region and a parity cell region including a first sub parity region and a second sub parity region. The interface circuit receives main data and sub data comprising external parity or a data mask signal, generates a flag signal based on mask bits of the data mask signal, performs ECC encoding operation on the main data in response to an operation mode and the flag signal, stores the main data in the normal cell region, stores either the external parity or the flag signal in the second sub parity region in response to the operation mode, performs an ECC decoding operation on the main data read from the normal cell region in response to the operation mode and the flag signal.

Abstract: A preparation method of a superabsorbent polymer, and a superabsorbent polymer prepared thereby are provided. The preparation method of the superabsorbent polymer according to the present disclosure prevents polymer particles from being broken or the surface thereof from being damaged during preparation and handling of the superabsorbent polymer, thereby providing a superabsorbent polymer having excellent absorption properties and permeability.

Abstract: The present invention relates to a method for purifying polyalkylene carbonate. More specifically, a method for purifying polyalkylene carbonate is provided, which uses a multistage extraction column having the number of stages of at least 10 stages, using water for effectively removing by-products such as alkylene carbonate generated in a process for producing polyalkylene carbonate resin, thereby controlling the content of by-products to a certain level or less through a continuous operation, particularly, the extraction is performed at room temperature, thereby easily removing by-products in the resin without a high temperature volatilization.

Abstract: A memory cell array may include a normal cell array and a spare cell array, the normal cell array having a plurality of normal memory cells connected to normal lines and the spare memory cell array having a plurality of spare memory cells connected to spare lines configured to replace a failed normal memory cell with a spare memory cell. A spare line address encoding circuit may be configured to generate a spare line address which encodes spare line enable signals being applied when a spare line replacing a normal line is activated to indicate a physical location of the spare line being activated. A spare line adjacent address generator may be configured to generate spare line adjacent address based on the spare line address, and to activate spare lines physically adjacent to the activated spare line.

Abstract: A memory device includes a memory cell array that includes a plurality of memory cell rows; and a refresh address generator configured to store flags respectively corresponding to the plurality of memory cell rows, generate refresh row addresses respectively corresponding to the plurality of memory cell rows by performing a count operation, and according to the flags, change a refresh period of the plurality of memory cell rows.

Abstract: A method of preparing a polyalkylene carbonate resin is provided. More particularly, a method of preparing a polyalkylene carbonate resin capable of preventing polymer degradation and improving physical properties and quality of a final resin product, in which, after polymerization of polyalkylene carbonate, by-products are removed by using a large amount of water to purify a reaction mixture, and in a subsequence process of removing a catalyst residue, a primary purification method is conducted by using a filter so that a content of the catalyst in the reaction mixture is less than 1% by weight, is provided.

Abstract: The present invention relates to a sensing method using machine learning. A sensing method according to the present invention comprises the steps of: providing a stimulus multiple times to a random position on a material for generating a detectable signal in response to an external stimulus; performing machine learning by using the signal generated through the stimuli; and predicting a location or degree of a stimulus which is provided to the material, by using a function derived through the machine learning.

Abstract: A touch window according to one embodiment comprises: a substrate having an effective area and an ineffective area; a sensing electrode arranged in the effective area and sensing a position; and a wiring arranged in the effective area and the ineffective area and electrically connecting to the sensing electrode, wherein the wiring comprises a first wiring and a second wiring such that the first wiring and the second wiring are vertically arranged.