Abstract: Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.

Abstract: A method of preparing a polyalkylene carbonate resin is provided. More particularly, a method of preparing a polyalkylene carbonate resin capable of preventing polymer degradation and improving physical properties and quality of a final resin product, in which, after polymerization of polyalkylene carbonate, by-products are removed by using a large amount of water to purify a reaction mixture, and in a subsequence process of removing a catalyst residue, a primary purification method is conducted by using a filter so that a content of the catalyst in the reaction mixture is less than 1% by weight, is provided.

Abstract: A device, system, and/or method includes an internal circuit configured to perform at least one function, an input-output terminal set and a repair circuit. The input-output terminal set includes a plurality of normal input-output terminals connected to an external device via a plurality of normal signal paths and at least one repair input-output terminal selectively connected to the external device via at least one repair signal path. The repair circuit repairs at least one failed signal path included in the normal signal paths based on a mode signal and fail information signal, where the mode signal represents whether to use the repair signal path and the fail information signal represents fail information on the normal signal paths. Using the repair circuit, various systems adopting different repair schemes may be repaired and cost of designing and manufacturing the various systems may be reduced.

Abstract: A semiconductor memory device includes a plurality of memory banks in a first region, a data terminal to which an input data signal is input, the data terminal being in a second region, and an inverting circuit that inverts or non-inverts the input data signal in response to an inversion control signal indicating whether the input data signal has been inverted, wherein at least one inverting circuit is disposed for each of the plurality of memory banks.

Abstract: A stacked semiconductor device includes a plurality of semiconductor dies and a plurality of thermal-mechanical bumps. The semiconductor dies are stacked in a vertical direction. The thermal-mechanical bumps are disposed in bump layers between the semiconductor dies. Fewer thermal-mechanical bumps are disposed at a location near a heat source included in the semiconductor dies than at other locations, or a structure of the thermal-mechanical bumps at the location near the heat source is different from a structure of the thermal-mechanical bumps at other locations.

Abstract: This disclosure relates to a resin composition that comprises polyalkylene carbonate, polylactide, polyalkyl(meth)acrylate, and cellulose, and has excellent biodegradability and mechanical properties, and yet, exhibits excellent thermal stability. Thus, the resin composition according to the present invention may be used in various application fields such as various films, sheets, disposable products, electronic goods, and interior material for automobiles.

Abstract: A touch panel according to the embodiment includes a substrate including an effective area and a dummy area surrounding the effective area; and an outer dummy layer in the dummy area; a planar layer on the substrate; and a transparent electrode disposed on the substrate to detect a position.

Abstract: Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.

Abstract: A semiconductor memory device includes a plurality of memory banks in a first region, a data terminal to which an input data signal is input, the data terminal being in a second region, and an inverting circuit that inverts or non-inverts the input data signal in response to an inversion control signal indicating whether the input data signal has been inverted, wherein at least one inverting circuit is disposed for each of the plurality of memory banks.

Abstract: A semiconductor memory device includes a memory cell array, a repair control circuit and a refresh control circuit. The memory cell array includes a plurality of memory cells and a plurality of redundancy memory cells. The repair control circuit receives a repair command and performs a repair operation on a first defective memory cell among the plurality of memory cells during a repair mode. The semiconductor memory device may operate in a repair mode in response to the repair command. The refresh control circuit performs a refresh operation on non-defective ones of the plurality of memory cells during the repair mode.

Abstract: In a method of operating a memory device, a command and a first address from a memory controller are received. A read code word including a first set of data corresponding to the first address, a second set of data corresponding to a second address and a read parity data is read from a memory cell array of the memory device. Corrected data are generated by operating error checking and correction (ECC) using an ECC circuit based on the read cord word.

Abstract: The present invention relates to a oriented film having excellent mechanical physical properties and more improved flexibility and elongation to be preferably usable as a packaging film, and the like, wherein the oriented film includes: a lactide copolymer including two or more block copolymer repeating units in which hard segments of polylactide repeating units are bound to both ends of soft segments of polyether polyol repeating units, the block copolymer repeating units being linked with each other, and a slope of a stress-strain curve at a section having a strain of 0 to 16% is 0.5 to 1.1.

Abstract: A semiconductor memory device includes a memory cell array, a repair control circuit and a refresh control circuit. The memory cell array includes a plurality of memory cells and a plurality of redundancy memory cells. The repair control circuit receives a repair command and performs a repair operation on a first defective memory cell among the plurality of memory cells during a repair mode. The semiconductor memory device may operate in a repair mode in response to the repair command. The refresh control circuit performs a refresh operation on non-defective ones of the plurality of memory cells during the repair mode.

Abstract: A system and method for automatically adjusting electrical performance of a radio frequency (RF) coil assembly of a magnetic resonance imaging (MRI) system during a medical imaging process of a subject to control changes in loading conditions of the RF coil caused by the subject during the medical imaging process.

Abstract: A semiconductor memory device includes a plurality of memory banks in a first region, a data terminal to which an input data signal is input, the data terminal being in a second region, and an inverting circuit that inverts or non-inverts the input data signal in response to an inversion control signal indicating whether the input data signal has been inverted, wherein at least one inverting circuit is disposed for each of the plurality of memory banks.

Abstract: A memory device may include a pre-charge control circuit, an active control circuit, and a driver circuit. The pre-charge control circuit may be configured to receive an active command after receiving a pre-charge command for a first bank, determine whether or not a pre-charge operation for the first bank has ended when receiving the active command, and generate an active instruction signal according to a result of the determination. The active control circuit may be configured to generate an active control signal for an active operation according to the active instruction signal. The driver circuit may be configured to control an active operation according to the active control signal.

Abstract: A semiconductor memory device includes a memory cell array, a repair control circuit and a refresh control circuit. The memory cell array includes a plurality of memory cells and a plurality of redundancy memory cells. The repair control circuit receives a repair command and performs a repair operation on a first defective memory cell among the plurality of memory cells during a repair mode. The semiconductor memory device may operate in a repair mode in response to the repair command. The refresh control circuit performs a refresh operation on non-defective ones of the plurality of memory cells during the repair mode.

Abstract: A touch window according to one embodiment comprises: a substrate having an effective area and an ineffective area; a sensing electrode arranged in the effective area and sensing a position; and a wiring arranged in the effective area and the ineffective area and electrically connecting to the sensing electrode, wherein the wiring comprises a first wiring and a second wiring such that the first wiring and the second wiring are vertically arranged.

Abstract: A semiconductor memory device includes a plurality of memory banks in a first region, a data terminal to which an input data signal is input, the data terminal being in a second region, and an inverting circuit that inverts or non-inverts the input data signal in response to an inversion control signal indicating whether the input data signal has been inverted, wherein at least one inverting circuit is disposed for each of the plurality of memory banks.

Abstract: The present invention relates to a lactide copolymer having excellent general physical properties such as mechanical physical properties, processability, and the like, and having excellent flexibility to be effectively usable as a packaging material, and the like, a preparing method thereof, and a resin composition including the same, wherein the lactide copolymer includes: two or more block copolymer repeating units in which hard segments of polylactide repeating units are bound to both ends of soft segments of polyether polyol repeating units, the block copolymer repeating units are linked with each other via a urethane linking group induced from a polyvalent isocyanate compound having more than 2 to less than 3 equivalents of an isocyanate group per a molecule, and the polyether polyol repeating unit has a number average molecular weight of 1000 to 10000.