Abstract: The present technology relates to a reference point marking apparatus for marking reference points on a pattern electrode in which coated portions and uncoated portions are repeatedly arranged in a longitudinal direction, in which the pattern electrode includes a plurality of reserved electrode lane parts to be slit into a plurality of electrode lanes in the longitudinal direction in a subsequent process, and the reference point marking apparatus includes a moving marking machine configured to mark reference points on uncoated portions of the reserved electrode lane parts arranged in a width direction of the pattern electrode while moving in the width direction, and a controller configured to control an operation of the moving 10 marking machine. The present technology also provides a roll map generation apparatus using the reference point marking apparatus.

Abstract: According to the present invention, there is provided A method of encoding a three-dimensional (3D) image, the method comprising: determining a prediction mode for a current block as an inter prediction mode; determining whether a reference block corresponding to the current block in a reference picture has motion information; when the reference block has the motion information, deriving motion information on the current block for each sub prediction block in the current block; and deriving a prediction sample for the current block based on the motion information on the current block.

Abstract: The present invention relates to a composition for promoting myogenesis, containing, as an active ingredient, a processed ginseng extract in which a trace amount of a ginsenoside ingredient is increased. It has been ascertained that the processed ginseng extract promotes the differentiation of myoblasts into muscle and inhibits muscle atrophy caused by myostatin, which is a myogenesis inhibitory factor, and thus it is expected that a composition for preventing or treating muscle disorder-related diseases, having excellent effects, can be developed.

Abstract: A gate driver includes a first scan signal generator configured to output a logic voltage for driving of a scan transistor through a plurality of stages connected in cascade, the scan transistor performing a switching operation to transfer a data voltage to a driving transistor of a pixel, a second scan signal generator configured to output a logic voltage for driving of a sensing transistor through the plurality of stages, the sensing transistor sensing deterioration of a light emitting element of the pixel, a light emission control signal generator configured to output a logic voltage for control of a light emission control transistor of the pixel through the plurality of stages, and an initialization voltage generator driven by logic voltages received from some nodes of the first scan signal generator based on the light emission control signal generator to supply an initialization voltage to the pixel.

Abstract: Systems and methods for manufacturing a battery are disclosed. One system may include: a first cutter configured to cut a first electrode sheet into a first electrode portion; a second cutter configured to cut a second electrode sheet into a second electrode portion having a second length; a winder configured to form an electrode assembly by winding the first electrode portion, the second electrode portion, a separator between the first electrode portion and the second electrode portion; and an identification information assigning device configured to assign identification information to the electrode assembly based on: a cut count value of the first electrode sheet and/or a cut count value of the second electrode sheet; and/or a position coordinate value of the first electrode sheet and/or a position coordinate value of the second electrode sheet.

Abstract: A semiconductor device includes an alignment data generation circuit aligning first and second latch data generated from a first group of input data in synchronization with a first internal strobe signal, outputting the aligned first and second latch data as first alignment data, aligning a first and second latch data generated from a second group of the input data in synchronization with a second internal strobe signal, and outputting the aligned first and second latch data as second alignment data. The semiconductor device includes a write data generation circuit generating first and second write data from the first and second alignment data in synchronization with a latch clock after the start of a first operation mode and generating the first and second write data from the first alignment data in synchronization with the latch clock after the start of a second operation mode.

Abstract: A lower rail for a seat of a vehicle has a structure with a curved movement path, in which the seat may be moved in an oblique direction or a diagonal direction according to various seat positions, thereby allowing a degree of freedom for adjusting a seat position movement. In addition, the lower rail includes a curved inner channel bent at a predetermined angle and a curved outer channel bent at about a same angle as the curved inner channel, which are separately provided and configured to be mutually combined in order to provide one curved movement path for moving the seat.

Abstract: A seat rail retainer includes a body, among a first rail and a second rail that are disposed to slide straightly respectively in a longitudinal direction, the body being fixed to the first rail, an elastic supporting portion protruding from the body to be elastically pressed by the second rail, and an inserting body inserted into the body to provide an elastic force to the elastic supporting portion.

Abstract: A muscular strength assisting apparatus includes a muscular strength assisting portion that assists a user's muscular strength and a first connecting link including one side connected to one side of the muscular strength assisting portion and an opposite side rotatable relative to a shoulder of the user about a first rotation axis. The muscular strength assisting portion includes an upper arm module that assists muscular strength of an upper arm of the user and a link assembly including one side connected to one side of the upper arm module to be rotatable about a second rotation axis non-parallel to the first rotation axis and an opposite side disposed adjacent to a portion of a body of the user to be supported on the user.

Abstract: A method according to an embodiment of the present invention corresponds to a method for transmitting, by a gateway, a synchronization signal block (SSB) through a plurality of satellites, and may comprise the steps of: determining satellite identification SSBs for identifying a plurality of satellites, respectively; determining beam identification SSBs for identifying beams usable for the plurality of satellites, respectively; and controlling the satellite identification SSBs and the beam identification SSBs to be transmitted to the plurality of satellites, respectively, through a predetermined resource, wherein the satellite identification SSBs and each of the beam identification SSBs have different SSB indices from each other.

Abstract: Disclosed herein are a duty cycle monitoring method and apparatus for a memory interface, including receiving a clock signal as input and generating a first delay time offset and a second delay time offset, receiving the clock signal and the first delay time offset and then outputting a first delayed signal, receiving the first delayed signal and the second delay time offset and then outputting a second delayed signal, receiving the clock signal and the second delayed signal and then outputting a delay value corresponding to a half-period of the clock signal, and monitoring, based on the first delayed signal, whether a duty cycle of the clock signal conforms to a duty cycle specification.

Abstract: The present invention relates to a method for transmitting a synchronization signal block (SSB) through a plurality of satellites from a base station that can connect to a plurality of gateways, wherein the method may comprise the steps of: controlling transmission of first SSBs corresponding to the number of beams of each satellite through respective transmission beams in a first SSB cycle; determining a transmission beam of each of the satellites on the basis of a first measurement report for the respective beams received from a terminal; and controlling transmission of second SSBs for determining one combination including two or more gateways among the plurality of gateways in a second SSB cycle.

Abstract: A semiconductor device includes an alignment data generation circuit aligning first and second latch data generated from a first group of input data in synchronization with a first internal strobe signal, outputting the aligned first and second latch data as first alignment data, aligning a first and second latch data generated from a second group of the input data in synchronization with a second internal strobe signal, and outputting the aligned first and second latch data as second alignment data. The semiconductor device includes a write data generation circuit generating first and second write data from the first and second alignment data in synchronization with a latch clock after the start of a first operation mode and generating the first and second write data from the first alignment data in synchronization with the latch clock after the start of a second operation mode.

Abstract: A memory may include a data transmission/reception circuit and a memory bank including a plurality of cell arrays. When a metadata mode is activated, data and metadata received through the data transmission/reception circuit may be distributed to and stored in the plurality of cell arrays. When the metadata mode is deactivated, the data received through the data transmission/reception circuit may be distributed to and stored in cell arrays except one or more no-access cell arrays, among the plurality of cell arrays.

Abstract: A memory module may include a management bus and a plurality of memories connected in series and connected to the management bus, each of the plurality of memories including an identification (ID) input terminal and an ID output terminal. Among the plurality of memories, a memory, for which an activation signal is applied to an ID input terminal of the memory, may set an ID for the memory in response to ID setting information transmitted on the management bus.

Abstract: A memory may include multiple rows each coupled to multiple memory cells; a target row classification circuit suitable for classifying, as a target row, a row, among the multiple rows, that is susceptible to data loss as a result of activity of an adjacent row; and a target row signal generation circuit suitable for sequentially activating a target row active signal for activating the target row and a target row precharge signal for precharging the target row in response to a precharge command.

Abstract: The present invention relates to a thiobenzimidazole derivative or a pharmaceutically acceptable salt thereof, and a composition for preventing or treating cancer, comprising the derivative as an active ingredient. The thiobenzimidazole derivative of the present invention exhibits cell toxicity by blocking the cell cycle of a cancer cell and inducing apoptosis when administered to an individual, as the derivative inhibits tubulin polymerization by being activated in the cancer cell, and, thus, the derivative can be used for prevention or treatment of cancer, desirably for prevention or treatment of triple-negative breast cancer.

Abstract: A semiconductor device includes an alignment data generation circuit aligning first and second latch data generated from a first group of input data in synchronization with a first internal strobe signal, outputting the aligned first and second latch data as first alignment data, aligning a first and second latch data generated from a second group of the input data in synchronization with a second internal strobe signal, and outputting the aligned first and second latch data as second alignment data. The semiconductor device includes a write data generation circuit generating first and second write data from the first and second alignment data in synchronization with a latch clock after the start of a first operation mode and generating the first and second write data from the first alignment data in synchronization with the latch clock after the start of a second operation mode.

Abstract: A memory device includes a memory cell array and a peripheral circuit. The memory cell array includes a plurality of memory regions each identified by a row address and a column address. The peripheral circuit accesses the memory cell array by performing, based on an address, a burst length and a burst address gap provided from a memory controller, a burst operation supporting a variable burst address gap. The burst address gap is a numerical difference between adjacent column addresses, on which the burst operation is to be performed.

Abstract: A memory device includes a memory cell array and a peripheral circuit. The memory cell array includes a plurality of memory regions each identified by a row address and a column address. The peripheral circuit accesses the memory cell array by performing, based on an address, a burst length and a burst address gap provided from a memory controller, a burst operation supporting a variable burst address gap. The burst address gap is a numerical difference between adjacent column addresses, on which the burst operation is to be performed.