Abstract: A semiconductor device may include an internal command pulse generation circuit and a sense data generation circuit. The internal command pulse generation circuit may generate an internal command pulse from a write signal based on an offset code and an internal clock signal. The sense data generation circuit may generate sense data from an internal data strobe signal based on the internal command pulse. The internal command pulse may be generated by delaying the write signal by a shift period based on the internal clock signal. The shift period may be controlled by the offset code.

Abstract: A paste for solar cell electrodes includes a conductive powder, a glass frit, and an organic vehicle. The glass frit includes bismuth (Bi), tellurium (Te), and antimony (Sb), and has a mole ratio of bismuth (Bi) to tellurium (Te) of about 1:1 to about 1:30.

Abstract: A semiconductor apparatus may be provided. The semiconductor apparatus may include a fine training circuit configured to generate a fine result signal based on a clock signal, a data strobe signal, and a command. The semiconductor apparatus may include a coarse training circuit configured to generate a coarse result signal based on the clock signal, the data strobe signal, and the command and to set an offset of a write enable signal based on an offset control signal.

Abstract: A semiconductor device includes a shift register and a control signal generation circuit. The shift register generates shifted pulses, wherein a number of the shifted pulses is controlled according to a mode of a burst length. The control signal generation circuit generates a control signal for setting a burst operation period according to a period during which the shifted pulses are created. The burst operation period is a period during which a burst operation is performed.

Abstract: A multi-subscriber identification module (SIM) device is provided, and includes first and second SIMs, first and second radio frequency (RF) resources, and a baseband processor. The first and second SIMs are for using first and second services of first and second networks respectively. The first RF resource supports a non-limiting channel configuration use in accordance with a radio resource control (RRC) protocol. The second RF resource supports a limiting channel configuration use in accordance with the RRC protocol. The baseband processor, in a dual radio (DR) mode, configures one of the first and second SIMs as a main SIM based on information on the first and second networks, allots the first RF resource to the main SIM, configures the other one as a sub-SIM, and allots the second RF resource to the sub-SIM.

Abstract: In an information processing method performed in a first gateway device among a plurality of gateway devices for managing a plurality of nodes, a current characteristic value recorded in a first node of the plurality of nodes is replaced with a new characteristic value. Then, a database is updated so that the database stores new information on the first node to which the new characteristic value is reflected. The new information on the first node is transmitted to another gateway device of the plurality of gateway devices.

Abstract: A semiconductor device may be provided. The semiconductor device may include a period code generation circuit configured to generate a period code having a logic level combination corresponding to a first command or a second command. The semiconductor device may include a code synthesis circuit configured to add the period code to a previous synthesis code to generate a synthesis code. The semiconductor device may include a buffer control circuit configured to compare the synthesis code with a selection control code to generate a buffer inactivation signal for controlling input of a data strobe signal.

Abstract: A semiconductor apparatus may be provided. The semiconductor apparatus may include a fine training circuit configured to generate a fine result signal based on a clock signal, a data strobe signal, and a command. The semiconductor apparatus may include a coarse training circuit configured to generate a coarse result signal based on the clock signal, the data strobe signal, and the command and to set an offset of a write enable signal based on an offset control signal.

Abstract: A semiconductor device includes a control circuit configured to generate a data reset signal which is enabled in response to a reset signal and first and second transfer control signals which are sequentially enabled in synchronization with a divided clock in response to a read signal and a trigger circuit configured to drive a driving signal depending on a logic level of latch data in synchronization with delayed clocks in response to the first and second transfer control signals, the driving signal having a fixed logic level based on the data reset signal being enabled.

Abstract: A method includes performing a first write leveling training operation and performing a second write leveling training operation. The first write leveling training operation is performed to generate transmission data based on a data strobe signal and an internal command pulse and to generate a latency code. The second write leveling training operation is performed to generate the transmission data based on the data strobe signal and the internal command pulse.

Abstract: A composition for forming an electrode includes a conductive powder, a glass frit, an organic vehicle, and a burn-out retardant. The burn-out retardant exhibits a residual carbon of greater than or equal to about 1 wt % at a temperature of about 600° C. based on the initial amount of 100 wt % and an exothermic peak at about 200° C. to about 500° C.

Abstract: A semiconductor device includes an internal command pulse generation circuit and a sense data generation circuit. The internal command pulse generation circuit is configured to generate an internal command pulse based on a write signal, a latency code, and an offset code. The sense data generation circuit is configured to generate a sense data based on the internal command pulse and an internal data strobe signal and configured to generate the sense data based on the internal command pulse and a delayed strobe signal.

Abstract: A semiconductor device includes a control circuit configured to generate a data reset signal which is enabled in response to a reset signal and first and second transfer control signals which are sequentially enabled in synchronization with a divided clock in response to a read signal and a trigger circuit configured to drive a driving signal depending on a logic level of latch data in synchronization with delayed clocks in response to the first and second transfer control signals, the driving signal having a fixed logic level based on the data reset signal being enabled.

Abstract: A semiconductor device includes a shift register and a control signal generation circuit. The shift register generates shifted pulses, wherein a number of the shifted pulses is controlled according to a mode of a burst length. The control signal generation circuit generates a control signal for setting a burst operation period according to a period during which the shifted pulses are created. The burst operation period is a period during which a burst operation is performed.

Abstract: A composition for solar cell electrodes includes silver powder, a glass frit, and an organic vehicle. The glass frit includes a first glass frit and a second glass frit. The first glass frit includes tellurium (Te) and silver (Ag) in a molar ratio (Te:Ag) of about 75:1 to about 1:25. The second glass frit includes a lead-tellurium-oxide (Pb—Te—O)-based glass frit or a bismuth-tellurium-oxide (Bi—Te—O)-based glass frit and is free from silver (Ag).

Abstract: A composition for solar cell electrodes and a solar cell electrode fabricated using the composition, the composition including a conductive powder; a glass frit; and an organic vehicle, wherein the glass frit has a reaction index (RI) of about 0.5 to about 1.0, as calculated according to Equation 1: Reaction index (RI)=Ib/Ia??<Equation 1> wherein, in Equation 1, Ia denotes a maximum peak intensity measured on a specimen at 20.5° to 20.7° (2?) by XRD analysis, the specimen being obtained by mixing the glass frit with Si3N4 powder in a weight ratio of 1:1 to prepare pellets, followed by heat-treatment at 800° C. for 10 minutes, and Ib denotes a maximum peak intensity measured on the specimen at 20.75° to 20.95° (2?) by XRD analysis.

Abstract: A semiconductor device may include an internal command pulse generation circuit and a sense data generation circuit. The internal command pulse generation circuit may generate an internal command pulse from a write signal based on an offset code and an internal clock signal. The sense data generation circuit may generate sense data from an internal data strobe signal based on the internal command pulse. The internal command pulse may be generated by delaying the write signal by a shift period based on the internal clock signal. The shift period may be controlled by the offset code.

Abstract: A semiconductor device may include an internal command pulse generation circuit and a sense data generation circuit. The internal command pulse generation circuit may generate an internal command pulse from a write signal based on an offset code and an internal clock signal. The sense data generation circuit may generate sense data from an internal data strobe signal based on the internal command pulse. The internal command pulse may be generated by delaying the write signal by a shift period based on the internal clock signal. The shift period may be controlled by the offset code.

Abstract: Disclosed herein is a composition for solar cell electrodes. The composition includes silver powder; glass frits; and an organic vehicle, wherein the glass frits have a glass transition temperature of about 100° C. to about 300° C. and exhibit an exothermic peak starting temperature of about 200° C. to about 400° C. on a DTA curve in TG-DTA analysis. Solar cell electrodes formed of the composition have high open circuit voltage and short circuit current density, thereby providing excellent conversion efficiency and fill factor.

Abstract: A semiconductor device may be provided. The semiconductor device may include a period code generation circuit configured to generate a period code having a logic level combination corresponding to a first command or a second command. The semiconductor device may include a code synthesis circuit configured to add the period code to a previous synthesis code to generate a synthesis code. The semiconductor device may include a buffer control circuit configured to compare the synthesis code with a selection control code to generate a buffer inactivation signal for controlling input of a data strobe signal.