Abstract: A cylindrical secondary battery module includes: a plurality of cylindrical secondary battery cells respectively having a battery case in which an electrode assembly and an electrolyte are accommodated; a cell frame at which the plurality of cylindrical secondary battery cells are disposed; and a lid coupled to the cell frame and having a flame outlet. The cell frame includes: a plurality of plate members bent and coupled to intersect each other; and a space formed between the plurality of plate members so that the cylindrical secondary battery cells are disposed therein.

Abstract: A FINFET includes a first fin extending in a first direction on a substrate and, a second fin extending in the first direction and spaced apart from the first fin in the first direction. A third fin is provided with a long side shorter than long sides of the first fin and the second fin and is disposed between the first fin and the second fin. A first gate structure extends in a second direction different from the first direction and crosses the first fin. A device isolation layer is disposed on a lower sidewall of each of the first, second and third fins and is formed to extend in the first direction. An electrically insulating diffusion break region includes a first portion crossing between the first fin and the third fin, a second portion crossing between the second fin and the third fin, and a third portion disposed between the first portion and the second portion on the third fin. The diffusion break region extends in the second direction on the device isolation layer.

Abstract: A substrate processing method includes stacking a plurality of stack structures each including an insulating layer and a sacrificial layer, on one another. The method also includes generating a stair structure by etching the stack structures and generating a separation layer on a side surface of the stair structure. The method further includes removing the sacrificial layer and generating conductive word line structures in spaces from which the sacrificial layer is removed. The separation layer is provided between the conductive word line structures.

Abstract: A spoken language understanding apparatus according to embodiments of the present disclosure may include: a slot tagging module including: a morpheme analysis unit configured to analyze morphemes with respect to an uttered sentence, a slot tagging unit configured to tag slots corresponding to a semantic entity from a plurality of input tokens generated according to the analyzed morphemes, and a slot name conversion unit configured to convert phrases corresponding to the tagged slots into delexicalized slot names based on neighboring contextual information; and a language generation module configured to generate a combined sequence by combining the delexicalized slot names based on the plurality of input tokens.

Abstract: Disclosed are a semiconductor device and a manufacturing method thereof. According to the semiconductor device and the manufacturing method thereof according to exemplary embodiments of the present invention, after the dopant source layer is uniformly deposited on a channel layer of the device with the 3-dimensional vertical structure by the plasma-enhanced atomic layer deposition (PEALD) method, the deposited dopant source layer is heat-treated so that the dopants are diffused into the channel layer to function as charge carriers, thereby preventing the charges in the channel layer from being reduced. According to the exemplary embodiments of the present invention, the diffusion speed and concentration of the dopant may be controlled by forming the barrier layer between the channel layer and the dopant source layer.

Abstract: A method for making a dual temperature label having a face stock and a liner comprises using a first adhesive pattern applicator to apply a first adhesive to the line. The method includes transferring the first adhesive from the liner to the face stock via a first chill roller. A second adhesive pattern applicator is used to apply a second adhesive to the liner after the first adhesive has been transferred therefrom to the face stock. The face stock is brought in registry with the liner via a second chill roller to make the dual temperature label such that each of the first adhesive and the second adhesive is sandwiched between the face stock and the liner. The first adhesive is a hot temperature adhesive and the second adhesive is a cold temperature adhesive, or vice versa.

Abstract: Provided is a method of forming a thin film having a target thickness T on a substrate by an atomic layer deposition (ALD) method. The method includes n processing conditions each having a film growth rate that is different from the others, and determining a1 to an that are cycles of a first processing condition to an n-th processing condition so that a value of |T?(a1×G1+a2×G2+ . . . +an×Gn)| is less than a minimum value among G1, G2, . . . , and Gn, where n is 2 or greater integer, G1, . . . , and Gn respectively denote a first film growth rate that is a film growth rate of the first processing condition, . . . and an n-th film growth rate that is a film growth rate of the n-th processing condition, and the film growth rate denotes a thickness of a film formed per a unit cycle in each of the processing conditions. The film forming method may precisely and uniformly control a thickness of the thin film when an ALD is performed.

Abstract: A method of processing a substrate to enable selective doping without a photolithography process is provided. The method includes forming a diffusion barrier on the substrate having a patterned structure using plasma deposition method, removing the diffusion barrier except for part of the diffusion barrier using wet etching, forming a diffusion source layer on the patterned structure and the part of the diffusion barrier, and applying energy to the diffusion source layer.

Abstract: A battery pack includes a first battery with a first capacity, a second battery with a second capacity less than the first capacity, and a variable resistor. The second battery has a larger maximum discharge current than the first battery. The variable resistor circuit limits the discharge current of the first battery to a predetermined limit current value.

Abstract: A passivation surface treatment method of stainless steel that improves corrosion resistance including in a brine environment without changing the appearance of the surface of stainless steel. A passivation surface treatment method for stainless steel includes: performing degreasing of stainless steel, performing electrolytic pickling where the stainless steel that underwent the degreasing is immersed in a pickling solution having phosphoric acid (H3PO4) and is connected to the anode and a voltage of about 0.5 to 5.0 V for about 10 seconds or more is applied, performing electrolytic degreasing of the stainless steel, and performing electrolytic passivation where the stainless steel that underwent the electrolytic degreasing is immersed in a passivation solution including dichromic acid and chromium sulfate and a voltage of about 0.5 to 5.0 V is applied for 5 seconds or more.

Abstract: A semiconductor device includes a low-density substrate, a high-density patch positioned inside a cavity in the low-density substrate, a first semiconductor die, and a second semiconductor die. The first semiconductor dies includes high-density bumps and low-density bumps. The second semiconductor die includes high-density bumps and low-density bumps. The high-density bumps of the first semiconductor die and the high-density bumps of the second semiconductor die are electrically connected to the high-density patch. The low-density bumps of the first semiconductor die and the low-density bumps of the second semiconductor die are electrically connected to the low-density substrate.

Abstract: A semiconductor device includes a substrate having a first active pattern and a second active pattern, the first active pattern including a first recess region dividing an upper portion thereof into a first portion and a second portion, the second active pattern including a second recess region dividing an upper portion thereof into a first portion and a second portion, a first insulating pattern covering an inner sidewall of the first recess region, and a second insulating pattern covering an inner sidewall of the second recess region. The first insulating pattern and the second insulating pattern include the same insulating material, and a volume fraction of the first insulating pattern with respect to a volume of the first recess region is smaller than a volume fraction of the second insulating pattern with respect to a volume of the second recess region.

Abstract: The present invention relates to a vesicle containing a saccharide isomerate, a hydrolyzed lupine protein, and an intercorneocyte lipid mimetics as an active ingredient, and a composition for skin external application including the vesicle, and more particularly, to a vesicle including: an aqueous phase part including a saccharide isomerate and a hydrolyzed lupine protein; and an oil phase part including an intercorneocyte lipid mimetics, lysolecithin, and glycerin. The vesicle includes the intercorneocyte lipid mimetics together with the saccharide isomerate and the hydrolyzed lupine protein as contents, so that the vesicle is excellent in a skin barrier recovery function and a skin moisturizing effect upon skin application. In addition, the vesicle is excellent in phase stability, so that the vesicle is suitable to be commercialized as various compositions for skin external application.

Abstract: A semiconductor manufacturing method includes depositing a low-k dielectric layer, forming a trench in the low-k dielectric layer, forming a barrier layer in the trench, filling a metal on the barrier layer, planarizing the metal, and forming a capping layer on the planarized metal, wherein the capping layer includes at least two layers.

Abstract: A semiconductor device is disclosed that may include a first semiconductor die comprising a copper pillar, a second semiconductor die comprising a copper pillar, and a conductive bump connecting the copper pillar of the first semiconductor die to the copper pillar of the second semiconductor die. The first semiconductor die may comprise a metal dam formed between the copper pillar and a bond pad on the first semiconductor die. The conductive bump may have a melting point lower than melting points of the copper pillar of the first semiconductor die and the copper pillar of the second semiconductor die. The first semiconductor die may be coupled to a substrate with a conductive wire coupled to the bond pad and to the substrate. The first semiconductor die may comprise a redistribution layer formed beneath the copper pillar on the first semiconductor die.

Abstract: The present invention relates to a composite separation membrane including a graphene oxide coating layer. The composite separation membrane of the present invention has both high carbon dioxide permeability and high selectivity for carbon dioxide over nitrogen, hydrogen or methane gas, is free of surface defects, and exhibits remarkably increased selectivity for carbon dioxide over other gases (hydrogen, nitrogen, methane, etc.) without any change in carbon dioxide permeability, particularly even when exposed to water. Due to these advantages, the composite separation membrane of the present invention can be applied to industrial fields involving carbon dioxide separation and recovery processes. The present invention also relates to a method for manufacturing the composite separation membrane.

Abstract: A method of processing a substrate by omitting a photolithographic process is disclosed. The method includes forming at least one layer on a stepped structure having an upper surface, a lower surface, and a side surface that connects the upper surface to the lower surface, selectively densifying portions of the at least one layer respectively on the upper surface and the lower surface via asymmetric plasma application, and performing an isotropic etching process on the at least one layer. During the isotropic etching process, the portion of the at least one layer formed on the upper surface is separated from the portion of the at least one layer formed on the lower surface.

Abstract: An electronic device is provided. The electronic device includes a display, a processor, and a memory storing a first application program including a first user interface and a second application program including a second user interface. The memory stores instructions that, when executed, cause the processor to display an array of icons in an area adjacent to the edge in response to the gesture input, wherein each of the icons has a first size, one of the icons includes a first icon and a second icon, the first icon and second icon having a second size smaller than the first size, the first icon indicates the first application program, and the second icon indicates the second application program, receive an input to select the one of the icons, and display the first user interface and the second user interface together on the display in response to the received input.

Abstract: A semiconductor device includes a substrate with a NMOS region and a PMOS region, a device isolation layer on the substrate to define active fins, and gate patterns on the substrate to have a length direction crossing the active fins, wherein the device isolation layer includes diffusion brake regions between respective pairs of the active fins, the diffusion brake regions being disposed adjacent to each other in a width direction of the gate patterns, and wherein a width of the diffusion brake region in the NMOS region is different from a width of the diffusion brake region in the PMOS region.

Abstract: The present invention relates to a method for fine-tuning gene expression levels using a synthetic regulatory sRNA in a prokaryotic cell. The present invention can simultaneously, easily, and quickly apply various target gene combinations to various strains without gene deletion through the synthetic regulatory sRNA for regulating gene expression and is therefore very suitable for measuring the metabolizability of each strain and selecting an optimum strain. In addition, the method has the advantages of easily and quickly selecting a target gene for the inhibition of gene expression and expressing the gene thus selected to a desired degree and thus can be used in producing recombinant strains for the efficient production of various metabolites and establishing a method for the efficient production and is therefore very useful.