Abstract: A method of depositing and etching dielectric layers having low dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects. The amount of carbon or hydrogen in the dielectric layer is varied by changes in deposition conditions to provide low k dielectric layers that can replace etch stop layers or conventional dielectric layers in damascene applications. A dual damascene structure having two or more dielectric layers with dielectric constants lower than about 4 can be deposited in a single reactor and then etched to form vertical and horizontal interconnects by varying the concentration of a carbon:oxygen gas such as carbon monoxide. The etch gases for forming vertical interconnects preferably comprises CO and a fluorocarbon, and CO is preferably excluded from etch gases for forming horizontal interconnects.

Abstract: A multichip assembly includes semiconductor devices or semiconductor device components with outer connectors on peripheral edges thereof. The outer connectors are formed by creating via holes along boundary lines between adjacent, unsevered semiconductor devices, or semiconductor device components, then plating or filling the holes with conductive material. When adjacent semiconductor devices or semiconductor device components are severed from one another, the conductive material in each via between the semiconductor devices is bisected. The semiconductor devices and components of the multichip assembly may have different sizes, as well as arrays of outer connectors with differing diameters and pitches. Either or both ends of each outer connector may be electrically connected to another aligned outer connector or contact area of another semiconductor device or component. Assembly in this manner provides a low-profile stacked assembly.

Abstract: A method of fabricating a flash memory cell having a split gate structure. A sacrificial layer is formed on a floating gate layer formed on a semiconductor substrate. The sacrificial layer is etched to form an opening exposing a portion of the floating gate layer. A gate interlayer insulating layer pattern is formed inside the opening. After removing the sacrificial layer pattern and etching the floating gate layer (using the gate interlayer insulating layer pattern as an etch mask), a floating gate is formed under the gate interlayer insulating layer pattern. A control gate is formed overlapping a portion of the floating gate.

Abstract: An apparatus and method for cathodic protection in an environment where thin film corrosive fluids are formed is provided. The apparatus which protects from corrosion an object exposed to the thin film corrosive fluids, by artificially adjusting a potential of the object, comprises a DC power supply of which cathode is electrically connected to the object to be corrosion-protected, and an anodic assembly of which anode is electrically connected to the DC power supply.

Abstract: A semiconductor device having a measuring pattern that enhances measuring reliability and a method of measuring the semiconductor device using the measuring pattern. The semiconductor device includes a semiconductor substrate having a chip area in which an integrated circuit is formed, and a scribe area surrounding the chip area. The semiconductor device also includes a measuring pattern formed in the scribe area and having a surface sectional area to include a beam area in which measuring beams are projected, and a dummy pattern formed in the measuring pattern to reduce the surface sectional area of the measuring pattern. The surface sectional area of the dummy pattern occupies from approximately 5% to approximately 15% of a surface sectional area of the beam area.

Abstract: A microelectronic component package includes a plurality of electrical leads which are coupled to a microelectronic component and which have exposed lengths extending outwardly beyond a peripheral edge of an encapsulant. A plurality of terminals may be positioned proximate a terminal face of the encapsulant and these terminals may be electrically coupled to the same leads. This can facilitate connection of the microelectronic component to a substrate using the leads as a conventional leaded package. The terminals, however, can facilitate stacking of the leaded package with one or more additional microelectronic components, e.g., a BGA package.

Abstract: The invention discloses a radio frequency identification system, comprising: a radio frequency identification tag having an identification code and a set of verifiable data stored therein; and a radio frequency identification reader which sends a reading request to the radio frequency identification tag, requesting to read a first portion of the set of verifiable data, wherein the radio frequency identification tag further comprising control means, which, when the radio frequency identification tag receives the reading request from the radio frequency identification reader, in case of that the set of verifiable data has not been performed a locking operation, performs the locking operation on the set of verifiable data, so that from then on any data of a second portion of the set of verifiable data cannot be read.

Abstract: In a method of manufacturing a non-volatile memory device, a first gate insulation layer and a conductive layer are formed on a substrate and then the conductive layer is partially oxidized to form an oxide layer pattern. The conductive layer is partially etched using the oxide layer pattern as an etching mask to form a floating gate electrode on the first gate insulation layer and then the silicon layer is formed on the substrate including the floating gate electrode. The silicon layer is oxidized to form a tunnel insulation layer and a second gate insulation layer on a sidewall of the floating gate electrode and on a surface portion of the substrate adjacent to the floating gate electrode and then a control gate electrode is formed on the tunnel insulation layer and the second gate insulation layer.

Abstract: A nozzle structure for a high-pressure spray head includes a nozzle and a nozzle head. The nozzle is made of iron in a concave shape. The nozzle head is disposed in the nozzle. The nozzle head includes a glass ring and a ceramic ring. The ceramic ring comprises an outlet therein. The nozzle and the ceramic ring are combined together by means of the glass ring.

Abstract: Methods of forming a semiconductor assembly are described which include a leadframe with leads having offset portions exposed at an outer surface of a material package to form a grid array. An electrically conductive compound, such as solder, may be disposed or formed on the exposed lead portions to form a grid array such as a ball grid array (“BGA”) or other similar array-type structure of dielectric conductive elements. The leads may have inner bond ends including a contact pad thermocompressively bonded to a bond pad of the semiconductor chip to enable electrical communication therewith and a lead section with increased flexibility to improve the thermocompressive bond. The inner bond ends may also be wirebonded to the bond pads.

Abstract: Disclosed is an LED device, a method for manufacturing the same, and a light emitting apparatus having the same. The LED device includes (a) a light emitting diode unit and (b) an adjustment layer laminated on a light emitting surface of the light emitting diode unit, a fine pattern having being formed on the adjustment layer by repeating a shape in a light emission direction. The adjustment layer is (i) at least one layer formed by aligning transparency adjustment particles having a shape or (ii) a polymer film layer having a fine pattern imprinted on the polymer film layer so as to adjust transparency. A fine pattern adjustment layer having various shapes and an adjustable size is introduced on the light emitting surface of the LED unit. As a result, the light extraction efficiency of the surface of the LED unit improves together with ease of manufacturing and secured uniformity.

Abstract: A fuse circuit can include a cut-off unit circuit configured to electrically isolate a fuse from an input to a status information circuit after latching of status information associated with status of the fuse. Other fuse related circuits and methods are disclosed.

Abstract: A method for fabricating an LED having section grown on a sapphire substrate, a boded structure, and a unit chip separated from the bonded structure. The method includes (a) bonding the section grown on a first surface of the sapphire substrate to a first surface of a first substrate with a first binder; (b) bonding a second surface of the first substrate to a first surface of a second substrate with a second binder; (c) removing the second substrate from a bonded structure obtained as a result of step (b) after polishing a second surface of the sapphire substrate; (d) separating the bonded structure into unit chips after the second substrate has been removed; and (e) bonding the second surface of the polished sapphire substrate provided in each unit chip to a lead frame, and removing the first substrate. This method improves heat dissipation efficiency.

Abstract: A light emitting diode devic that includes (a) a light emitting diode section, (b) an electrically conductive pad section being disposed outside the light emitting diode section and being electrically connected to an external power source, and (c) at least one electrically conductive interconnection section for connecting the electrically conductive pad section to one side or both sides of the light emitting diode section. In the light emitting diode device, a wire is connected to the electrically conductive pad section disposed outside the light emitting diode section, and the electrically conductive pad section is connected to one side of the light emitting diode section by means of at least one electrically conductive interconnection section, so that not only it is easy to uniformly coat a fluorescent substance, but also an area covering vertically emitted light can be reduced to enhance a light extraction efficiency of the light emitting diode device.

Abstract: There is provided a method of fabricating a split-gate flash memory cell using a spacer oxidation process. An oxidation barrier layer is formed on a floating gate layer, and an opening to expose a portion of the floating gate layer is formed in the oxidation barrier layer. Subsequently, a spacer is formed on a sidewall of the opening with a material layer having insulation property by oxidizing, and an inter-gate oxide layer pattern between a floating gate and a control gate is formed in the opening while the spacer is oxidized by performing an oxidation process.

Abstract: A semiconductor device package is disclosed which is substantially die-sized with respect to each of the X, Y and Z axes. The package includes outer connectors that are located along at least one peripheral edge thereof and that extend substantially across the height of the peripheral edge. Each outer connector is formed by severing a conductive via that extends substantially through a substrate blank, such as a silicon wafer, at a street located adjacent to an outer periphery of the semiconductor device of the package. The outer connectors may include recesses that at least partially receive conductive columns protruding from a support substrate therefor. Assemblies may include the packages in stacked arrangement, without height-adding connectors.

Abstract: The invention relates to a framework system and methods for connecting a plurality of tools. The system comprises a plug-in mechanism configured to dynamically load the plurality of tools, a data pool having storage space configured to store data sets associated with the plurality of tools, a linking mechanism configured to establish communications links between the loaded plurality of tools to enable coordinated operation of the loaded plurality of tools, a session component configured to record the process history of the operations of the loaded plurality of tool and the system states corresponding to the process history of the operations and an annotation module configured to associate user-provided data corresponding to one or more of the stored data sets.

Abstract: This invention provides a dictionary learning method, said method comprising the steps of: learning a lexicon and a Statistical Language Model from an untagged corpus; integrating the lexicon, the Statistical Language Mode and subsidiary word encoding information into a small size dictionary. And this invention also provides an input method on a user terminal device using the dictionary with Part-of-Speech information and a Part-of-Speech Bi-gram Model added, and a user terminal device using the same. Therefore, sentence level prediction and word level prediction can be given by the user terminal device and the input is speeded up by using the dictionary which is searched by a Patricia Tree index of a dictionary index.

Abstract: An apparatus and method for cathodic protection in an environment where thin film corrosive fluids are formed is provided. The apparatus which protects from corrosion an object exposed to the thin film corrosive fluids, by artificially adjusting a potential of the object, comprises a DC power supply of which cathode is electrically connected to the object to be corrosion-protected, and an anodic assembly of which anode is electrically connected to the DC power supply.

Abstract: A hanger for an electronic apparatus. The hanger comprises a base mounted to a wall, a bracket pivoting on the base, a first link pivoting on the base and comprising a ratchet with a plurality of teeth, and a second link with a stopper rotatably connecting the first link and the bracket. The angle between the bracket and the base is varied by the stopper engaging each tooth of the ratchet. The bracket can rotate between a first position and a second position. When the bracket is in the first position, the bracket overlaps the base, and in the second position, the angle between the bracket and the base is maximized.