Abstract: A method for joining a metal component with a connection, wherein the metal component has a hole, the metal component is placed in an inner channel of a metal plate, and using a head type punch metal of the metal plate is forced into the corresponding hole of the metal component thereby joining the metal plate and the metal component with the press-fit connection.

Abstract: A semiconductor assembly includes a leadframe with leads having offset portions exposed at an outer surface of a material package to form a grid array. An electrically conductive compound, such as solder, may be disposed or formed on the exposed lead portions to form a grid array such as a ball grid array (“BGA”) or other similar array-type structure of dielectric conductive elements. The leads may have inner bond ends including a contact pad thermocompressively bonded to a bond pad of the semiconductor chip to enable electrical communication therewith and a lead section with increased flexibility to improve the thermocompressive bond. The inner bond ends may also be wirebonded to the bond pads. Components for and methods of forming semiconductor assemblies are included.

Abstract: A microelectronic component package includes a plurality of electrical leads which are coupled to a microelectronic component and which have exposed lengths extending outwardly beyond a peripheral edge of an encapsulant. A plurality of terminals may be positioned proximate a terminal face of the encapsulant and these terminals may be electrically coupled to the same leads. This can facilitate connection of the microelectronic component to a substrate using the leads as a conventional leaded package. The terminals, however, can facilitate stacking of the leaded package with one or more additional microelectronic components, e.g., a BGA package.

Abstract: Methods, systems, and computer program products for high-performance interprocess communication. Each process dynamically identifies routines responsible for managing communication received from other processes through a shared memory heap and a shared memory queue, each of the routines handling one or more operation codes. An allocation from the shared heap produces a process agnostic memory handle from which a process specific memory pointer may be obtained. Using the memory pointer, the enqueuing process places an operation code, parameters, and any other relevant data in the allocated memory and adds the memory handle to a shared queue. The dequeuing process removes the memory handle from the queue and generates a memory pointer to access the allocated memory in the dequeuing process. Upon retrieving the operation code from the allocated memory, the dequeuing process calls the appropriate handler routine. Enqueues may be registered to account for expected responses that are not received.

Abstract: Packaged microelectronic devices and methods of packaging microelectronic devices are disclosed herein. In one embodiment, the device includes an image sensor die having a first side with a bond-pad, an active area on the first side, and a second side opposite the first side. The device further includes a window at the first side of the image sensor die and a lead mounted to the second side of the image sensor die. The window is radiation transmissive and positioned over the active area of the image sensor die. The lead is electrically coupled to the bond-pad on the image sensor die.

Abstract: A multichip assembly includes semiconductor devices or semiconductor device components with outer connectors on peripheral edges thereof. The outer connectors are formed by creating via holes along boundary lines between adjacent, unsevered semiconductor devices, or semiconductor device components, then plating or filling the holes with conductive material. When adjacent semiconductor devices or semiconductor device components are severed from one another, the conductive material in each via between the semiconductor devices is bisected. The semiconductor devices and components of the multichip assembly may have different sizes, as well as arrays of outer connectors with differing diameters and pitches. Either or both ends of each outer connector may be electrically connected to another aligned outer connector or contact area of another semiconductor device or component. Assembly in this manner provides a low-profile stacked assembly.

Abstract: The method of manufacturing a split gate flash memory device includes the steps of (a) providing a semiconductor substrate of a conductivity type opposite to that of a first junction region; (b) sequentially forming a first dielectric film, a first conductive film, a second dielectric film and a third dielectric film on an overall upper face of the substrate; (c) etching the third dielectric film by a given thickness so as to expose the second dielectric film; (d) removing the exposed second dielectric film, and eliminating the remaining third dielectric film; (e) etching the first conductive film and the second dielectric film by a given thickness so as to partially expose the first conductive line and the first conductive film; (f) forming a fourth dielectric film on a portion of the exposed first conductive line and first conductive film; (g) eliminating the remaining second dielectric film remained, and exposing the first conductive film provided in a lower part thereof; and (h) etching the first dielectr

Abstract: A semiconductor device having a trench isolation structure and a method of fabricating the same are provided. The device has a trench region and an isolation structure. The trench region is disposed to define an active region at a predetermined region of an SOI substrate formed by sequentially stacking a buried insulating layer and an upper silicon layer on a base substrate. The isolation structure fills an inside of the trench region. The trench region has a deep trench region where the upper silicon layer penetrates to the buried insulating layer and a shallow trench region existing at an outside of the deep trench region. The method of forming a trench region with deep and shallow trench regions includes patterning an upper silicon layer of an SOI substrate. A trench oxide layer and a trench liner are conformally formed on a sidewall and a bottom of the trench region.

Abstract: A method of fabricating a non-volatile memory device includes the steps of forming a lower conductive layer on a substrate, forming a lower and an upper sacrificial patterns on the substrate with the lower conductive layer, wherein the lower and upper sacrificial patterns include a trench exposing the lower conductive layer, forming mask spacers on sidewalls of the upper and lower sacrificial patterns, using the mask spacers and the upper sacrificial pattern as an etch mask, etching the exposed lower conductive layer to form a lower conductive pattern exposing the substrate, forming a plug conductive layer covering an entire surface of a substrate with the lower conductive pattern, and planarizingly etching the plug conductive layer until the lower sacrificial pattern is exposed, thereby forming a source plug in a gap region between the mask spacers that is connected to the substrate.

Abstract: A semiconductor device having a trench isolation structure and a method of fabricating the same are provided. The device has a trench region and an isolation structure. The trench region is disposed to define an active region at a predetermined region of an SOI substrate formed by sequentially stacking a buried insulating layer and an upper silicon layer on a base substrate. The isolation structure fills an inside of the trench region. The trench region has a deep trench region where the upper silicon layer penetrates to the buried insulating layer and a shallow trench region existing at an outside of the deep trench region. The method of forming a trench region with deep and shallow trench regions includes patterning an upper silicon layer of an SOI substrate. A trench oxide layer and a trench liner are conformally formed on a sidewall and a bottom of the trench region.

Abstract: A semiconductor device package is disclosed which is substantially die-sized with respect to each of the X, Y and Z axes. The package includes outer connectors that are located along at least one peripheral edge thereof and that extend substantially across the height of the peripheral edge. Each outer connector is formed by severing a conductive via that extends substantially through a substrate blank, such as a silicon wafer, at a street located adjacent to an outer periphery of the semiconductor device of the package. The outer connectors may include recesses that at least partially receive conductive columns protruding from a support substrate therefore. Assemblies may include the packages in stacked arrangement, without height-adding connectors.

Abstract: A semiconductor device having a trench isolation structure and a method of fabricating the same are provided. The device has a trench region and an isolation structure. The trench region is disposed to define an active region at a predetermined region of an SOI substrate formed by sequentially stacking a buried insulating layer and an upper silicon layer on a base substrate. The isolation structure fills an inside of the trench region. The trench region has a deep trench region where the upper silicon layer penetrates to the buried insulating layer and a shallow trench region existing at an outside of the deep trench region. The method of forming a trench region with deep and shallow trench regions includes patterning an upper silicon layer of an SOI substrate. A trench oxide layer and a trench liner are conformally formed on a sidewall and a bottom of the trench region.

Abstract: A semiconductor device package is disclosed which is substantially die-sized with respect to each of the X, Y and Z axes. The package includes outer connectors that are located along at least one peripheral edge thereof and that extend substantially across the height of the peripheral edge. Each outer connector is formed by severing a conductive via that extends substantially through a substrate blank, such as a silicon wafer, at a street located adjacent to an outer periphery of the semiconductor device of the package. The outer connectors may include recesses that at least partially receive conductive columns protruding from a support substrate therefor. Assemblies may include the packages in stacked arrangement, without height-adding connectors.

Abstract: A method of fabricating split gate type FLASH memory device comprises forming trench device isolation layers in a substrate to define a plurality of parallel first active regions. A gate insulation pattern, a conductive pattern and a hard mask pattern, which are sequentially stacked, are formed to have sidewalls aligned to sidewalls of the trench device isolation layer. Along each of the first active regions, the hard mask pattern is removed at regular intervals to expose a top of the conductive pattern. An oxide pattern is formed on the exposed top of the conductive pattern and the hard mask pattern is removed. Using the oxide pattern as an etch mask, the conductive pattern is etched to form floating gate patterns arranged over each of the first active regions at regular intervals. Tunnel oxide layers are formed on sidewalls of the floating gate patterns. A plurality of control gate electrodes are formed to cross over the first active regions.

Abstract: The present invention herein relates to method for joining metal component by press-fit connection characterized by hole of metal component place in inner channel of metal plate by using head type punch to forcing metal of metal plate into corresponding hole of metal component for joining metal plate and metal component with press-fit connection.

Abstract: The present invention herein relates to fastening structure for a heat sink to provide a fastening structure easy and convenient both for assembling and disassembling operation, characterized by fastening structure being a material of elasticity comprising a controlling member and a motioning member, wherein controlling member is composed of a reinforcing loop, a operational portion of controlling member and a first radian claw, a motioning member buckling up controlling member is composed of a operational portion of motioning member and a second radian claw, heat sink for assembling and disassembling operate in coordination with a first radian claw, a second radian claw and a reinforcing loop

Abstract: A microelectronic component package includes a plurality of electrical leads which are coupled to a microelectronic component and which have exposed lengths extending outwardly beyond a peripheral edge of an encapsulant. A plurality of terminals may be positioned proximate a terminal face of the encapsulant and these terminals may be electrically coupled to the same leads. This can facilitate connection of the microelectronic component to a substrate using the leads as a conventional leaded package. The terminals, however, can facilitate stacking of the leaded package with one or more additional microelectronic components, e.g., a BGA package.

Abstract: The method of manufacturing a split gate flash memory device includes the steps of (a) providing a semiconductor substrate of a conductivity type opposite to that of a first junction region; (b) sequentially forming a first dielectric film, a first conductive film, a second dielectric film and a third dielectric film on an overall upper face of the substrate; (c) etching the third dielectric film by a given thickness so as to expose the second dielectric film; (d) removing the exposed second dielectric film, and eliminating the remaining third dielectric film; (e) etching the first conductive film and the second dielectric film by a given thickness so as to partially expose the first conductive line and the first conductive film; (f) forming a fourth dielectric film on a portion of the exposed first conductive line and first conductive film; (g) eliminating the remaining second dielectric film remained, and exposing the first conductive film provided in a lower part thereof; and (h) etching the first dielectr

Abstract: The present invention provides a method for assembling heat sink fastening structure. Each of the components in the heat sink fastening structure is composed of elastic materials. The method includes the following steps: (A) first, forming a control lever and a relating lever in one-piece type, the control lever has an operating end, a positioning hole, two lock slots, a pressing ring, and a first gripping jaw; the relating lever has an operating end, a spring, two lock blocks, and a second gripping jaw; (B) second, pushing the two lock blocks up to two corresponding lock slots and making the spring sealed between the control lever and the relating lever; (C) finally, pushing the spring into the positioning hole and putting two lock blocks into two corresponding lock slots. Therefore, the heat sink fastening structure is assembled.