Abstract: In one example, a semiconductor package comprises a substrate having a top surface and a bottom surface, an electronic device mounted on the top surface of the substrate and coupled to one or more interconnects on the bottom surface of the substrate, a cover over the electronic device, a casing around a periphery of the cover, and an encapsulant between the cover and the casing and the substrate.

Abstract: The disclosure relates to a battery pack with a function of discharging venting gas and a control system for the same, in which air for cooling is allowed to flow during a normal state, and venting gas generated in a battery cell during thermal runaway is discharged outward from a vehicle but prevented from flowing back to a vehicle interior. The battery pack with a function of discharging venting gas includes an outlet duct including a channel selectively set to discharge air that returns from cooling a battery cell to an interior of a vehicle, or discharge venting gas that is generated due to thermal runaway of the battery cell to an outside of the vehicle; a switching wall provided inside the outlet duct, and setting a channel inside the outlet duct; and an actuator actuating the switching wall to discharge the venting gas to the outside of the vehicle when the thermal runaway occurs in the battery cell.

Abstract: In one example, a semiconductor package comprises a substrate having a top surface and a bottom surface, an electronic device mounted on the top surface of the substrate and coupled to one or more interconnects on the bottom surface of the substrate, a cover over the electronic device, a casing around a periphery of the cover, and an encapsulant between the cover and the casing and the substrate.

Abstract: A flow meter for a sewage conduit according to the present invention includes a first body portion, which is a portion inserted into the sewage conduit, comprising a plurality of sets of fluid induction portions that are formed to face each other at regular intervals from a lowest water depth close to a bottom surface of the sewage conduit to less than a highest water depth and protrude along an inner circumferential surface in parallel in a flow direction, and a pair of ultrasonic transducers that are embedded in protruding sides end of the fluid induction portions, designed in a V method so that ultrasonic waves emitted from one ultrasonic transducer are reflected by the fluid induction portions facing each other and reach the other ultrasonic transducer, and configured to increase a separation distance from a low water depth to a high water depth; a second body portion, which is a portion exposed to the outside of the sewage conduit by extending toward a manhole from the first body portion inserted into th

Abstract: A display device including a substrate, a plurality of gate bus lines and a plurality of data bus lines intersecting the plurality of gate bus lines on the substrate, a plurality of pixel regions arranged between the plurality of data bus lines and the plurality of gate bus lines on the substrate, a plurality of pixel electrodes on the substrate at each of the plurality of pixel regions; and a plurality of microlenses over the substrate, wherein at least three microlenses among the plurality of microlenses correspond to each of the pixel electrodes in a width direction of the each of the pixel electrodes, wherein at least three microlenses correspond to edge portions of each of the pixel electrodes, and wherein at least one microlens among the plurality of microlenses that is overlapped with one data bus line does not overlap with the other data bus lines.

Abstract: A method and apparatus for image conversion according to an embodiment of the present disclosure includes receiving original image data, separating the original image data into a front view image and a back view image for performing 3D conversion processing of the original image data, and generating a converted 3D image by restoring a background space between the front view image and the back view image using a 3D conversion processing neural network. The 3D conversion processing neural network according to the present disclosure may be a deep neural network generated by machine learning, and input and output of images may be performed in an Internet of things environment using a 5G network.

Abstract: A method and apparatus for image conversion according to an embodiment of the present disclosure includes receiving original image data, separating the original image data into a front view image and a back view image for performing 3D conversion processing of the original image data, and generating a converted 3D image by restoring a background space between the front view image and the back view image using a 3D conversion processing neural network. The 3D conversion processing neural network according to the present disclosure may be a deep neural network generated by machine learning, and input and output of images may be performed in an Internet of things environment using a 5G network.

Abstract: In one example, a semiconductor package comprises a substrate having a top surface and a bottom surface, an electronic device mounted on the top surface of the substrate and coupled to one or more interconnects on the bottom surface of the substrate, a cover over the electronic device, a casing around a periphery of the cover, and an encapsulant between the cover and the casing and the substrate.

Abstract: A display device including a substrate, a plurality of gate bus lines and a plurality of data bus lines intersecting the plurality of gate bus lines on the substrate, a plurality of pixel regions arranged between the plurality of data bus lines and the plurality of gate bus lines on the substrate, a plurality of pixel electrodes on the substrate at each of the plurality of pixel regions; and a plurality of microlenses over the substrate, wherein at least three microlenses among the plurality of microlenses correspond to each of the pixel electrodes in a width direction of the each of the pixel electrodes, wherein at least three microlenses correspond to edge portions of each of the pixel electrodes, and wherein at least one microlens among the plurality of microlenses that is overlapped with one data bus line does not overlap with the other data bus lines.

Abstract: In one example, a semiconductor package comprises a substrate having a top surface and a bottom surface, an electronic device mounted on the top surface of the substrate and coupled to one or more interconnects on the bottom surface of the substrate, a cover over the electronic device, a casing around a periphery of the cover, and an encapsulant between the cover and the casing and the substrate.

Abstract: A display device includes first and second transparent substrates; a plurality of gate bus lines and data bus lines on the first transparent substrate to define a plurality of pixels; a plurality of color filter layers under the second transparent substrates; and a plurality of microlenses under one of the first and second transparent substrates at positions corresponding to the gate and data bus lines, wherein at least two microlenses among the plurality of microlenses are corresponded to each of the gate or data bus lines in a width direction of each of the gate or data bus lines, and wherein a border between the at least two microlenses is substantially aligned with a center of a corresponding one of the gate and data bus lines, and wherein at least one microlens overlapped with one data bus line does not overlap with the other data bus lines.

Abstract: In one example, a semiconductor package comprises a substrate having a top surface and a bottom surface, an electronic device mounted on the top surface of the substrate and coupled to one or more interconnects on the bottom surface of the substrate, a cover over the electronic device, a casing around a periphery of the cover, and an encapsulant between the cover and the casing and the substrate.

Abstract: The present invention relates to a polyester resin composition and a molded article produced therefrom. The polyester resin composition includes: about 80 wt % to about 98 wt % of a polybutylene terephthalate resin; about 0.1 wt % to about 5 wt % of a carbodiimide-based compound; about 0.1 wt % to about 5 wt % of a nucleating agent; and about 0.5 wt % to about 15 wt % of an inorganic filler having a non-spherical or non-circular cross-section.

Abstract: A display device includes first and second transparent substrates; a plurality of gate bus lines and data bus lines on the first transparent substrate to define a plurality of pixels; a plurality of color filter layers under the second transparent substrates; and a plurality of microlenses under one of the first and second transparent substrates at positions corresponding to the gate and data bus lines, wherein at least two microlenses among the plurality of microlenses are corresponded to each of the gate or data bus lines in a width direction of each of the gate or data bus lines, and wherein a border between the at least two microlenses is substantially aligned with a center of a corresponding one of the gate and data bus lines, and wherein at least one microlens overlapped with one data bus line does not overlap with the other data bus lines.

Abstract: A liquid crystal display with a high transmittance and a low power consumption rate, includes first and second transmittable substrates, a plurality of gate and data bus lines formed on the first substrate, a plurality of color filters formed on the second substrate, and a plurality of microlenses formed on the first or second substrate corresponding to the gate and data bus lines. The microlenses are formed at positions corresponding to the gate and data bus lines which block incident lights, so that most incident lights can be transmitted. Further, the transmittance can be greatly improved by forming the microlenses at the positions corresponding to storage capacitor lines as well as the gate and data bus lines.

Abstract: Disclosed is a method for updating an inverted index of a flash solid state disk (SSD). The method including: storing postings of a term that is present in only an in-memory inverted index in a block of an output buffer and reading postings of a last block of each posting list to be updated from an on-disk inverted index to be stored in each block of an input buffer, by scanning the on-disk inverted index and the in-memory inverted index; moving postings of the input buffer to the blocks of the output buffer for each block and attaching new postings of the in-memory inverted index to the block corresponding to the output buffer; and updating the on-disk inverted index by using the postings of each block of the output buffer.

Abstract: A negative capacitance logic device includes a first field effect transistor (FET) and a second FET. The first FET is coupled between a power supply voltage and an output node, and the first FET includes a ferroelectric having a negative capacitance. The second FET is coupled between the output node and a ground voltage, and the second FET includes a ferroelectric having a negative capacitance. The negative capacitance logic differentiates an input voltage applied to an input node to provide an output voltage at the output node.

Abstract: A negative capacitance logic device includes a first field effect transistor (FET) and a second FET. The first FET is coupled between a power supply voltage and an output node, and the first FET includes a ferroelectric having a negative capacitance. The second FET is coupled between the output node and a ground voltage, and the second FET includes a ferroelectric having a negative capacitance. The negative capacitance logic differentiates an input voltage applied to an input node to provide an output voltage at the output node.

Abstract: Example embodiments are related to a high power spin torque oscillator that is integrated by combining a transistor. The high power spin torque oscillator according to example embodiments may include a spin torque oscillator and a transistor. The spin torque oscillator may perform an oscillation function and a transistor may perform an amplification function by integrating the spin torque oscillator and a transistor in one chip. The transistor may amplify an amplification signal of the spin torque oscillator. The high power spin torque oscillator may be integrated on FET or BJT.

Abstract: Example embodiments are related to a high power spin torque oscillator that is integrated by combining a transistor. The high power spin torque oscillator according to example embodiments may include a spin torque oscillator and a transistor. The spin torque oscillator may perform an oscillation function and a transistor may perform an amplification function by integrating the spin torque oscillator and a transistor in one chip. The transistor may amplify an amplification signal of the spin torque oscillator. The high power spin torque oscillator may be integrated on FET or BJT.